Effect of double-layered Al2O3/SiO2 dielectric materials on In–Ga–Zn–O(IGZO)-based amorphous transparent thin film transistors

Park, Chan-Rok; Hwang, Jin‐Ha

doi:10.1016/j.ceramint.2014.04.151

Cited by 18 publications

(8 citation statements)

References 15 publications

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“…Among all the high-k materials, AlO x and HfO x are the most common GIs of reported bottom-gate OS TFTs. [35,36,38] In order to investigate the ultrathin high-k GI based on TG structure, Figure 2a,b compares the transfer characteristics of the 3M-proposed SATG a-IGZO TFTs with GIs of 4-nm AlO x and HfO x , respectively. During the ALD process, water (H 2 O) or ozone (O 3 ) is used as the wet or dry oxidant, and (CH 3 ) 3 Al (TMA) or [(CH 3 ) 2 N] 4 Hf (TDMAHf) is adopted as the aluminum (Al) or hafnium (Hf) source, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Thus far, the SiO x GI of a-IGZO TFTs has been thinned down to 8.6 nm, [34] whereas it is still insufficient to cope with the sub-micro channel. An even thinner equivalent oxide thickness (EOT) demands the atomic layer deposited (ALD) high-k dielectrics, such as Al 2 O 3 , [35][36][37] HfO 2 , [38,39] ZrO 2 , [40] etc. However, the top-gate ALD GI readily causes the chemical reaction damages to underneath OS layers.…”

Section: Introductionmentioning

confidence: 99%

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3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

Zhang

et al. 2023

Adv Elect Materials

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The capacitor-less embedded dynamic random access memory (eDRAM) based on oxide semiconductor (OS) transistors exhibits a promising future and thus has lead to a growing demand for nanoscale OS thin-film transistors (TFTs). In this work, a self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) TFT is demonstrated by using the simplest 3-masks (3M) process, and the downscaling-related issues are carefully addressed to strengthen its back-end-of-line (BEOL) compatibility and mass producibility. The gate insulator (GI) and associated interface defects of the TFTs are jointly optimized with 4-nm atomic-layer-deposited (ALD) AlO x on the pre-oxidized a-IGZO. The defects in a-IGZO channel are further manipulated with a rapid thermal anneal (RTA) in oxygen. By virtue of the strengthened gate controllability and modified channel properties, the fabricated TFT with 97-nm gate length (L g ) exhibits decent performance, such as a maximum on-state current (I ON ) of 32.4 μA μm −1 , as well as clear linear and saturation characteristics. Based on such 3M SATG a-IGZO TFTs with high device performance and inherently minimal parasitic capacitances, the developed capacitor-less eDRAM bit cell achieves a wide sensing margin and a long retention time of over 500 s. A highly manufacturable oxide TFT technology for high-performance and high-density monolithic-3D (M3D) integration is thus well established.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

Zhang

et al. 2023

Adv Elect Materials

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“…When considering these lower annealing temperatures the IGZO properties are known to be strongly related to its processing conditions [12] and adjustment of the cation ratio 2 in the material thus plays a major role in its optimization [13]. In addition, employing dielectrics with high dielectric permittivity, ε r , (high-κ dielectrics) can compensate for poorer performances by reducing driving voltages (e.g., as required in power-efficient applications within IoT) and improving gate voltage swing due to higher gate capacitances [14,15]. For low temperature deposition of dielectrics, physical techniques such as pulsed laser deposition (PLD) [16,17], thermal evaporation [18,19] and sputtering can be used, the latter allowing the deposition of most materials without any intentional substrate heating [20], at a large scale and with low contamination [21].…”

Section: Introductionmentioning

confidence: 99%

Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Martins

Pinto

Rovisco

et al. 2020

Electronic Materials

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Co-sputtering of SiO2 and high-κ Ta2O5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO2 both mixed with Ta2O5 and as thin interfacial layers. A stack comprising a (Ta2O5)x(SiO2)100 − x film with x = 69 and a thin SiO2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µFE) ≈ 16 cm2·V−1·s−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 107. Anomalous Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 105 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.

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“…Layered dielectrics such as graphene oxide (GO) and other dielectrics are widely used as substrates and gate dielectrics to build different two-dimensional nanoscale devices, e.g., graphene-based vertical heterostructures [1], waveguide connectors [2], and thin film transistors [3]. Specifically, GO, a hydrophilic atomic sheet of graphite with oxygen functionalities, is a graphene-based dielectric which forms a layered assembly with an adjustable interlayer spacing at different humidity [4][5][6] due to absorbing water.…”

Section: Introductionmentioning

confidence: 99%

Electric-field-induced emergent electrical connectivity in graphene oxide

et al. 2019

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Understanding the appearance of local electrical connectivity in liquid filled layered graphene oxide subjected to an external electric field is important to design electrically controlled smart permeable devices and also to gain insight into the physics behind electrical effects on confined water permeation. Motivated by recent experiments [K. G. Zhou et al. Nature (London) 559, 236 (2018)], we introduce a new model with random percolating paths for electrical connectivity in micron thick water filled layered graphene oxide, which mimics parallel resistors connected across the top and bottom electrodes. We find that a strong nonuniform radial electric field of the order ∼10-50 mV/nm can be induced between layers depending on the current flow through the formed conducting paths. The maxima of the induced fields are not necessarily close to the electrodes and may be localized in the middle region of the layered material. The emergence of electrical connectivity and the associated electrical effects have a strong influence on the surrounding fluid in terms of ionization and wetting which subsequently determines the permeation properties.

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Effect of double-layered Al2O3/SiO2 dielectric materials on In–Ga–Zn–O(IGZO)-based amorphous transparent thin film transistors

Cited by 18 publications

References 15 publications

3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

Ta2O5/SiO2 Multicomponent Dielectrics for Amorphous Oxide TFTs

Electric-field-induced emergent electrical connectivity in graphene oxide

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