Effect of CoSi₂Formation Process on CMOS Transistor Electrical Properties for Sub-100-nm Memory Applications

Abstract

We investigated the effect of various processing conditions on abnormal CoSi 2 formation, such as the well-known Co spike and crystal agglomeration. We used Co metal sputtering and subsequent thermal treatment such as rapid thermal processing. The effect of the ion implantation conditions and Co deposition method were studied. To evaluate the electrical failure of transistors, we checked the chip level leakage current (I pp ), and the unit level leakage current (JLC) in the test pattern, simultaneously. As the dopant species and concentration were believed to affect the electrical properties of every single transistor, chip level leakage current and unit level leakage current deteriorate or improve simultaneously. When we used a Ti/TiN capping layer and high-temperature physical vapor deposition, abnormal growth was suppressed and the interface became smooth. The chip level leakage current in both cases showed significant improvement; however, the unit level leakage current showed a negligible change in contrast to the chip level one. We concluded that, despite no change in unit level leakage current, the overall level of chip level leakage current improved because of the significantly decreased number of defective sites such as Co spike. As complementary metal-oxide-semiconductor (CMOS) scaling occurs, the parasitic component of transistors, such as the external resistance (R ext ), plays an increasingly critical role in the overall electrical performance of transistors.1 Various components, which might be junctions, contacts, or metal interconnects, contribute to R ext . Most importantly, the contribution of R ext to degradation of metal contacts (the contact resistance) is the most serious problem, because the contact area decreases monotonously with feature size scaling of integrated circuits. Considering that the contact resistance is proportional to the resistivity ρ times the contact area A, we should reduce the resistivity significantly to meet the R ext requirement. However, the resistivity is also degraded with decreasing contact area owing to the well-known line width effect. 2The structural properties and formation behavior of cobalt silicide (CoSi 2 ) are of considerable practical interest for nano-electronic applications. Its high chemical inertness and thermal stability, together with its low resistivity, have promoted its use for metallization in integrated circuit fabrication.3-5 CoSi 2 has also been used for various Si-based applications such as buried CoSi 2 conducting patterns and a diffusion barrier and as a thermally stable metallization material for nanoparticles and nano-wires as well as compound semiconductors. [6][7][8] Most importantly, CoSi 2 is a promising candidate for addressing this R ext scaling issue because it is insensitive to the line width effect.It has been widely reported that the formation of cobalt silicide is directly affected by various surface states, such as the existence of silicon oxide and surface passivation.9-11 For this reason, extensive studies have been done ...

Quantitative Evaluation of Cobalt Disilicide/Si Interfacial Roughness

“…[2][3][4] CoSi 2 has been used for various electronic devices, such as memory electrode for 3D structure 5 and the metallization material for nanoparticles, nanowires 6,7 . As devices scale down, a thin, uniform CoSi 2 layer is essential for those nano-electronic applications.…”

“…1 Among various metal silicides, CoSi 2 is considered as an attractive contact material because of its low resistivity (10-20 μ • cm), no line-width dependence in narrow lines, and its superior chemical and thermal stability. [2][3][4] CoSi 2 has been used for various electronic devices, such as memory electrode for 3D structure 5 and the metallization material for nanoparticles and nanowires. 6,7 As devices scale down, a thin, uniform CoSi 2 layer is essential for those nano-electronic applications.…”