2014
DOI: 10.1063/1.4902963
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Effect of atomic layer deposition growth temperature on the interfacial characteristics of HfO2/p-GaAs metal-oxide-semiconductor capacitors

Abstract: Articles you may be interested inEffect of annealing ambient and temperature on the electrical characteristics of atomic layer deposition Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and MOSFETs

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Cited by 14 publications
(8 citation statements)
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References 34 publications
(29 reference statements)
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“…We controlled the ALD process circle to manufacture different dielectric thicknesses. A post-deposition annealing (PDA) process was applied to increase the quality of the oxide-semiconductor interface [14][15][16][17]. The process involved heating the film from ambient temperature to 380 • C in N 2 over 15 s, annealing for 60 s , and then cooling to ambient temperature over 300 s [6,7].…”
Section: Methodsmentioning
confidence: 99%
“…We controlled the ALD process circle to manufacture different dielectric thicknesses. A post-deposition annealing (PDA) process was applied to increase the quality of the oxide-semiconductor interface [14][15][16][17]. The process involved heating the film from ambient temperature to 380 • C in N 2 over 15 s, annealing for 60 s , and then cooling to ambient temperature over 300 s [6,7].…”
Section: Methodsmentioning
confidence: 99%
“…Pure nitrogen (99.999%) was used as a carrier gas and for purging the reactor after each reagent pulse. The well-known TEMAH+H 2 O precursor system was used (10)(11)(12). TEMAH was delivered into the reactor from the heated source at 100 °C.…”
Section: Experiments Detailsmentioning
confidence: 99%
“…Meanwhile, in order to suppress the increase of gate leakage current induced by the down-scaling of device dimensions, many high-k materials, e.g. HfO 2 [3], TiO 2 [4], La 2 O 3 [5], etc, have been employed as the gate dielectric of GaAs-based MOS devices. Among these high-k materials, zirconium dioxide (ZrO 2 ) has a high k value (∼24), large bandgap (∼5.8 eV) and sufficient band offsets versus GaAs (∼1.4 eV for the conduction band and ∼3.0 eV for the valence band) [6], therefore good device performance has been achieved by using it as the gate dielectric in GaAs MOS devices [7][8][9].…”
Section: Introductionmentioning
confidence: 99%