Effect of Arsenic Partial Pressure on Capless Anneal of Ion‐Implanted GaAs

Kasahara, J.; Arai, M.; Watanabe, Naozo

doi:10.1149/1.2128842

Cited by 22 publications

(8 citation statements)

References 7 publications

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“…For a crude approximation, ~ and Nv are written in the form (17) --~o exp (Kl~r) [4] Nv : N~o exp (K~-) [5] Subscript "o" represents each value in an unstrained crystal. Consequently in the strained crystal, the diffusion constant is rewritten as D = Do[1 + r -vs)/Es] ~ exp (KI~) exp (Kay) [6] Kt and K2 are constants. So far as our experiments are concerned, the factor coming from the change in the lattice constant was negligible because the magnitude of the external stress in our experiments were of the order of 10 .8 ~ 107 dyne/cm 2, and (1 --vs)/Es is much smaller than unity.…”

Section: Discussionmentioning

confidence: 99%

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The Effect of Stress on the Redistribution of Implanted Impurities in GaAs

Kasahara¹,

Kato²,

Arai³

et al. 1983

J. Electrochem. Soc.

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The stress introduced by the difference in thermal expansion coefficients between an encapsulant and a substrate was found to affect the redistribution of implanted impurities during annealing. Compressive stress introduced by an SigN4 film on GaAs enhanced the diffusion of implanted Si, Se, and S. Diffusion constants of Si and Se increased exponentially with the increase in the film thickness in a thickness region less than 0.1 ~m. The diffusion mechanism was discussed and it was concluded that the change in the jump frequency of diffusing atoms was dominant in determining the effect of stress in the damaged implantation layer. Excess of carriers was also observed in Se-and S-implanted samples, while deficit in carriers was observed in Si-implanted samples when the samples were subsequently annealed with an Si3N4 film. ~mall logic swing is essential for achieving a GaAs logic integrated circuit, particularly in ennancementmode logic circuits, where logic swing in Schottky barrier FETes should be 0.7V at most and that in junction FET's 1.2V to avoid appreciable gate current. Channel layers of both FET's are usually formed by ion implantation directly into a semi-insulating ~ubstrate. Variation of the carrier concentration profile in the ion-implanted channel layer over the whole wafer is a most crucial problem for uniformity and reproducibility of the devices. Precisely controlled ion-implanted layers are required to achieve GaAs integrated circuits.ion implantation technology is advantageous, because it can, in principle, control the profile for the channel layer only by changing the implantation energy and ion .dose. The profile is predicted by the LSS range statistics (1). A damaged layer by ion implantation, however, has to be annealed at high temperature in order to remove radiation damage and to activate implanted impurities as donors or acceptors. Implanted impurities are redistributed by diffusion during postimplantation annealing at high temperature. The factors affecting the redistribution were discussed previously by Kasahara and Watanabe (2) and Yoder (3). Thermal stress during post-implantation annealing was pointed out to be one of the factors, and the example was shown in the case of Zn ion implantation into GaAs (2). The effect of the thermal stress on the redistribution of Cr in Cr-doped semi-insulating substrates was also reported (4, 5). However, it is not clear how the stress influenced the redistribution of implanted impurities in GaAs.In this paper, the effect of the external stress on the redistribution of implanted Si, Se, and S in GaAs is investigated by using a wafer with thermal stress introduced by the .difference in the thermal expansion coefficient between an encapsulant and GaAs. Following the descriptions of the experimental conditions and the results, we discuss variations in the diffusion constants of implanted Si and Se under a wide range of external stress conditions. Variations in the doping efficiency of the implanted impurities are also described briefly as a function of the...

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Section: Discussionmentioning

confidence: 99%

“…All the samples were annealed in palladium-purified H2 under amine partial pressur~ of 3.0 Torr. Without an encapsulant (capless annealing), the samples were annealed in the face-to-face configuration described in a previous publication (6), while, with an encapsulant (capped annealing), the samples were annealed in the face-up configuration (6).…”

mentioning

confidence: 99%

The Effect of Stress on the Redistribution of Implanted Impurities in GaAs

Kasahara¹,

Kato²,

Arai³

et al. 1983

J. Electrochem. Soc.

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“…The authors have reported evidence of the decreasing As-vacancy in the GaAs with increasing arsenic pressure in the annealing ambient. 8 As is shown clearly in Fig. 1 plotted in Fig.…”

Section: Shallow P + Layer In Gaas Formed By Zinc Ion Implantationmentioning

confidence: 55%

Shallow p+ layer in GaAs formed by zinc ion implantation

Kasahara

Watanabe

1981

Applied Physics Letters

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A shallow p+ layer with a steep boundary was obtained by Zn ion implantation and a capless annealing in an arsenic ambient. A capped annealing with a plasma deposited Si3N4 film resulted in a carrier concentration profile broadened by the diffusion enhanced by the interfacial stress between the capping film and the semiconductor. The p+ layer had a peak carrier concentration of 8×1019 cm−3 and a thickness of less than 1000 Å. Arsenic pressure in the annealing ambient also suppressed the enhanced diffuison of Zn in the ion-implanted GaAs.

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“…The sample to be annealed was sandwiched between two GaAs wafers and placed in the sample carrier. An Arsenic overpressure was provided by the decomposition of the InAs found at the end of the furnace tube [5,6]. After the tube was purged the furnace was slid over the sample to begin annealing.…”

Section: Methodsmentioning

confidence: 99%

Rapid Thermal Anneal and Furnace Anneal of Silicon and Beryimlum Implanted Gallium Arsenide

1985

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A comparison has been made between rapid thermal annealing (RTA) and furnace annealing (FA) of implanted GaAs. Hall measurements showed consistently higher electrical activation of n-type (Si-5E12 cm -2) implants with FA and higher electrical activation of p-type (Be-1E14 cm -2) implants with RTA. Photoluminescence (PL) revealed that for RTA temperatures above 950 0 C some of the Si was going onto As, acceptor sites, thus reducing the net donor concentration. PL for RTA below 950'C showed signs of incomplete recrystallization. By a technique of "dual implantation" of As and Si into GaAs we were able to force the Si onto Ga-sites resulting in a higher donor concentration after RTA.

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Effect of Arsenic Partial Pressure on Capless Anneal of Ion‐Implanted GaAs

Cited by 22 publications

References 7 publications

The Effect of Stress on the Redistribution of Implanted Impurities in GaAs

The Effect of Stress on the Redistribution of Implanted Impurities in GaAs

Shallow p+ layer in GaAs formed by zinc ion implantation

Rapid Thermal Anneal and Furnace Anneal of Silicon and Beryimlum Implanted Gallium Arsenide

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