Effect of Annealing Ambient on Structural and Electrical Properties of Ge Metal-Oxide-Semiconductor Capacitors with Pt Gate Electrode and HfO<SUB>2</SUB> Gate Dielectric

Abstract

We fabricated Ge metal-oxide-semiconductor (MOS) devices with Pt/HfO 2 gate stacks and investigated the effect of thermal treatment on their structural and electrical properties in oxygen (O 2 ) and forming gas (FG) environments. The annealing ambient dependency of the structural and electrical properties of Ge MOS devices was directly compared to that of Si MOS devices. For both Ge and Si MOS devices, the thermal treatment process led to a decrease in accumulation capacitance regardless of the annealing ambient. The interfacial layer (IL) at the HfO 2 /Ge stack was much thinner than the HfO 2 /Si stack. O 2 annealing resulted in the improvement of the HfO 2 interfacial quality of Ge and Si MOS devices, although the improvement of the Ge devices was greater than that of the Si devices. FG annealing was much more effective in the reduction of interface state density (D it ) in Si devices than in Ge devices. A negligible IL at a HfO 2 /Ge stack could be a main cause of degraded electrical performance of a Ge device with FG annealing.

Thermal Atomic Layer Deposition of TaAlC with TaCl5and TMA as Precursors

“…Post deposition anneal was carried out at 450 • C in N 2 /O 2 to eliminate the oxygen vacancy in the bulk HfO 2 film and improve the film quality. [21][22][23] After that, 8 nm ALD TaAlC metal was grown as metal gate. Then 2 nm TiN by thermal ALD using TiCl 4 and NH 3 as precursors at 400 • C, and 75 nm ALD W using B 2 H 6 and WF 6 were deposited as top electrode.…”

Mixed high dielectric constant layers for MOS devices

“…Figure 3 shows the capacitance versus voltage characteristics of TZO dispersion and remarkable stretch in the entire depletion region with some kinks/bumps at starting and ending points of it. The acceptable reasons for these observations could be, large leakage currents, noticeable series resistance and higher order interface state density (D it ) level, respectively [15][16][17][18]. Besides, there was a remarkable negative shift in the at band voltage from standard at band voltage of MOS structure in as-deposited devices.…”

Forming Gas Post Metallization Annealing of Recessed AlGaN/GaN-on-Si MOSHFET

“…Since surface and interface states are strongly process-dependent, the gate insulator process must be carefully optimized. It was reported that the insulator itself and interface conditions between insulator and semiconductor surface could be improved by appropriate post-annealing processes [8][9][10][11][12]. In this study, we investigated the effects of forming gas post metallization annealing (PMA) on recessed AlGaN/GaN-on-Si MOSHFET with ICPCVD SiO 2 gate oxide.…”