Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Chen, Kuan-Ming; Henke, Wolfgang; Jung, Ji-Hoon; Kasperkiewicz, Ewa; Bouma, Anita; Rahman, Rizvi; Isai, Gratiela; Kim, Gwang-Gon; Tsiachris, Sotirios; Yoo, Jae-Doug; Park, Jinah; Park, JaeYoung; Won, Jonggeun; Oh, Nang-Lyeom; Chen, Hsin-Yu; Lin, WeiTai; Hsieh, Cheng-Yu; Pao, K.; Cho, Kyoyeon; Elmalk, Abdalmohsen; Raghunathan, Sudharshanan; Jee, Taekwon; Jeong, Seung-Uk; Jae, Jeongwoo; Kim, Sang Woo; Lee, Dongyoung; Kim, Jungchan; Ma, Won-Kwang; Lee, Sang-Ho; Park, Chanha

doi:10.1117/12.2584149

Cited by 4 publications

(3 citation statements)

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“…In this paper we focus on two layers (noted A and B layers) of an advanced DRAM node developed by SK hynix Inc [3], the schematic diagram of the layout is shown in Figure 1. The failure mode for EPE in this use case is the tips of A layer not covered by B layer from the top.…”

Section: Use Case Descriptionmentioning

confidence: 99%

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Ridane

Chen²,

Song³

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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For advanced nodes, a robust metrology is required to estimate EPE and its contributors. Especially when moving to late process development steps (Ramp-Up and High Volume Manufacturing (HVM)) where inter and intra wafer variations are small but crucial. In this study, we used 8um by 8um SEM images to assess the benefit of large Field-of-View (LFOV) metrology. The result proves the capability of LFOV metrology in capturing not only intra-wafer EPE behavior and its sensitivity to minor variations but also the minor wafer-to-wafer (W2W) variations which is not possible using a small FOV (SFOV) metrology (0.5um by 0.5um) due to larger noise level.

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Section: Use Case Descriptionmentioning

confidence: 99%

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Ridane

Chen²,

Song³

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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“…The edgeplacement error (EPE), which refers to the total vertical misalignment of features, has become an increasingly important metric in semiconductor manufacturing. Of all EPE metrics, on-product overlay appears to be one of the most crucial contributors [13,14], as it could be directly responsible for shorts or missing contacts within the integrated circuit and could therefore cause whole dies to malfunction, which in turn directly decreases process yields.…”

Section: Etch-induced Overlay Due To Sheath Deformationmentioning

confidence: 99%

Plasma sheath modelling to predict etch-induced overlay

Džafić¹,

Kamali²,

Venugopalan³

2021

J. Phys. D: Appl. Phys.

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In this work a two-dimensional, axisymmetric plasma sheath model is presented that is used to predict ion trajectory deviations in the plasma-wafer interface for a given set of physical etch conditions and chamber geometries. The model successfully predicts the plasma sheath deformation and the associated ion tilt in the vicinity of the wafer edge due to electrical discontinuities. We couple the predictive power of the plasma sheath model with a feature-scale kinetic Monte Carlo etch model to determine the asymmetries in post-etched structures and hence on-product overlay. The feature-scale model serves as a tool to translate the ion tilt within plasma sheath to the sidewall angle asymmetries in the etched trenches and the resulting overlay errors in two adjacent layers of a semiconductor device that could ultimately affect the device yield.

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“…For the better proxy to the yield or patterning excursion of the device, Edge Placement Error (EPE) was revisited and clarified as yield limiting metric [1], [5]- [8] . The metric is based on large statistics that combines all the variations both on CD and overlay domains: systematic, global, and local variations [6] .…”

Section: Introductionmentioning

confidence: 99%

Real time EPE measurement as a yield correlated metrology on advanced DRAM nodes

Jee,

You,

Lee

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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The Edge Placement Error (EPE) is growing concerns due to the complexity increases of process variation as the design rule shrinkage of DRAM device. The EPE is a well-accepted metric which can be derived from CD, Overlay and LER measurements from more than patterning layers that concerned [1] . Therefore, real time EPE measurement becomes a major factor to monitor and control the pattern fidelity.The pattern fidelity could be found from the edge placement measurement as a distance to design intent as possible without pattern defects. However, the traditional application of photolithography and etch biases according to a design rule or model for identifying pattern fidelity has inherent low TMU, multiple non consistence data sources and time-consuming off-line analysis.In previous works [2]-[4] , we demonstrated the innovative e-Beam EPE metrology application using All-In-One (AIO) methodology to comply the required Total Measurement Uncertainty (TMU) and Time to Result (TTR) on the advanced DRAM nodes. AIO imaging and analysis methodology that deconvolute CD, overlay and relevant EPE metrics from a single see-through image is the most important differentiation for this EPE analysis approach. The in-cell direct EPE measurement with All-In-One (AIO) imaging and massive sampling demonstrates the better process controls and monitoring from the co-optimization of multiple control parameters and direct measurement of the yield relevant metrics.In this paper, we would like to show a couple of EPE monitoring use cases which shows good correlation to the final yield map through the massive and multi-layer measurements. Especially, it is expected that the EPE component which measures the edge-to-edge distance between different features of multi-layers can be a useful indicator for predicting yield along with CD and overlay. To investigate the local and random variabilities, which local stochastic effects are contained, we also studied the degree of yield prediction of the EPE component with increasing number of measurement sites in local area. It is proposed that using a large amount of measurement sites allows to improve the yield prediction accuracy to a certain extent, which means the local stochastic effects can be effectively analyzed with the use of massive metrology approach. In addition, from the prediction accuracy study using EPE model-based machine learning, we proved that the EPE is sufficiently sensitive indicator to capture potential yield-loss problems in normal wafer, as well. Therefore, in-line EPE monitoring using AIO metrology enables the root-cause analysis of patterning weak points and provides a better process monitoring/correction solution to enable faster advanced DRAM node development ramp and high-volume stability.

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Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Cited by 4 publications

References 0 publications

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Plasma sheath modelling to predict etch-induced overlay

Real time EPE measurement as a yield correlated metrology on advanced DRAM nodes

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