Edge-Contact MoS₂ Transistors Fabricated Using Thermal Scanning Probe Lithography

Abstract

The science and engineering of two-dimensional materials (2DMs), in particular, of 2D semiconductors, is advancing at a thriving pace. It is well known that these delicate few-atoms thick materials can be damaged during the processing toward their integration into final devices. Thermal scanning probe lithography (t-SPL) is a gentle alternative to the typically used electron beam lithography to fabricate these devices avoiding the use of electrons, which are well known to deteriorate the 2DMs’ properties. Here, t-SPL is used for the fabrication of MoS2-based field effect transistors (FETs). In particular, the use of t-SPL is demonstrated for the first time for the fabrication of edge-contact MoS2 FETs, combining the hot-tip patterning and Ar+ milling to etch the 2DM. To avoid contamination of the contact interface by atmospheric gas molecules, etching and metal deposition are performed without breaking the vacuum conditions in between. With this process, edge-contact MoS2 FETs are successfully fabricated and characterized. On/off ratios up to 108 and 109 are obtained at room temperature in air and vacuum, respectively, i.e., comparable with the best values reported in the literature.

Promotion of Processability in a p-Type Thin-Film Transistor Using a Se–Te Alloying Channel Layer

“…44,45 Despite the Φ SB of 0.15 eV between the 250 °C-annealed Se 0.5 Te 0.5 and the Ni interface, the resulting TFT showed ohmic behavior, owing to such an edge contact effect. 46 As a practical application, we demonstrate a CMOS inverter using a p-type Se 0.5 Te 0.5 TFT and an n-type Al-doped InZnSnO TFT. Figure 6a illustrates the cross-sectional SEM and top-view optical microscopy image (inset of Figure 6a) of the n-channel TFT with a back-channel etched structure.…”

“…The valence band edges of as-deposited and 250 °C-annealed Se 0.5 Te 0.5 layers were approximately 0.45 eV, and the corresponding VBMs were 5.49 and 5.39 eV, respectively. The effective Schottky barrier height (Φ SB ) between the 250 °C-annealed Se 0.5 Te 0.5 channel layer and the Ni S/D electrode interface is shown in Figure S10. , Despite the Φ SB of 0.15 eV between the 250 °C-annealed Se 0.5 Te 0.5 and the Ni interface, the resulting TFT showed ohmic behavior, owing to such an edge contact effect …”

Patterned growth of two-dimensional atomic layer semiconductors

“…Some resists are sensitive to temperature, so the desired patterns can be synthesized based on thermal scanning probe lithography, resulting in thermal decomposition by the heated tip. 27 The spatial resolution and stability of the raw materials during the fabrication process determine the choice of patterned TMDC nanostructures obtained by lithography.…”

Thermal Scanning-Probe Lithography for Broad-Band On-Demand Plasmonic Nanostructures on Transparent Substrates

“…Previously published reports already highlighted the importance of t-SPL for developing contacts and interconnects to 2D-TMD-based devices and, in particular, described clearly the possibility to directly overlay the lithographic pattern on top of the ultrathin material , without using prealigned grids and energetic probes. Here, we instead focus our attention on a novel nanofabrication route that extends the current limitations of t-SPL-based approaches for nanophotonic applications.…”