Edge and bevel automated defect inspection for 300mm production wafers in manufacturing

Morillo, Jaime; Houghton, T.; Bauer, J.; Smith, Randy; Shay, R.

doi:10.1109/asmc.2005.1438766

Cited by 10 publications

(3 citation statements)

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“…Defect inspection concepts or technologies are under development or have to be realized within the next years. Currently, it is a key challenge to find a method for the root cause inspection of wafer edge and backside (30). Important criteria beside coverage of all areas, sensitivity and speed are ADC (automated defect classification and characterization) and optical review capability on the tool as well as a standard result file allowing SEM (secondary electron microscope) review.…”

Section: Inspection and Characterization Of The Wafer Edgementioning

confidence: 99%

Scenario for a Yield Model Based on Reliable Defect Density Data and Linked to Advanced Process Control

Nutsch

Oechsner

2006

ECS Trans.

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Currently, yield enhancement and APC (advanced process control) systems operate independently within the manufacturing process. Yield enhancement has several requirements such as the root cause analysis of yield loss, the reliability of defect density data, and the demand for a link between yield models and APC. For root cause studies chemical analysis uses different preparation techniques to describe the nature and location of contamination or defect densities, e.g. copper bulk contamination or wafer edge effects. The reliability of defect density data and the matching of defect inspection tools improve by the reduction of noise. In combination with a process model this is the prerequisite to set up a random defect-based yield scenario which describes single processes. The combination of this scenario with methods for data acquisition and tracking from APC enhances the prediction of yield.

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Section: Inspection and Characterization Of The Wafer Edgementioning

confidence: 99%

Scenario for a Yield Model Based on Reliable Defect Density Data and Linked to Advanced Process Control

Nutsch

Oechsner

2006

ECS Trans.

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“…As CMP (chemical mechanical polishing) process can not control the film status at bevel area, the bevel films normally consist of dielectric film, metal film and CMP residua. Besides the out-of-control uniformity, the poor adhesion among these films tends to lead to the peeling defect generation [1,2,3] . Three kinds of methods usually used to clean the bevel and wafer extreme edge area include bevel polishing, wet clean and plasma etch [3] .…”

Section: Introductionmentioning

confidence: 99%

The Reduction of Post Contact Glue Layer Peeling Defects in Gate Last Approach

Chenglong

Han

et al. 2014

ECS Trans.

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Gate last approach has started to appear in the high performance applications since 45nm technoology node. Such approach has to leverage the extra metal CMP (chemical mechanical polising) to planarize the working function metal and form the metal gate. However, it's well known that the metal CMP itself is incapable of controlling the performance at bevel area. Even worse, coupled with the instability of CMP residua, the non-optimized litho EBR process and the side-effect of integraton scheme, this poses the challenges for peeling defect control for the sake of the potential stress mismatch, the complex film stack at boundary and the weak adhesion among different film remainings at bevel area. This works aims to come up with one overall solution to post contact glue layer peeling issue including both dielectric film peeling and metallic film peeling at wafer edge area. Besides the selection of insert point and the selectivity optimzation for bevel etch, the adjustment of substrate, litho EBR and the control range of bevel etch are also proven imperative. The final over-all solution demonstrates both kinds of peeling defects could be remarkably alleviated, thus leading to yield enhancement.

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“…Recently, particle on the wafer bevel and the edge become serious defects that influence yield [1][2][3] . For instance, when a wafer is dipped in diluted hydro fluoric acid (DHF) with wet bench, particle on the wafer bevel and edge relocated to the wafer surface (Figure 1).…”

Section: Introductionmentioning

confidence: 99%