The Reduction of Post Contact Glue Layer Peeling Defects in Gate Last Approach

Abstract

Gate last approach has started to appear in the high performance applications since 45nm technoology node. Such approach has to leverage the extra metal CMP (chemical mechanical polising) to planarize the working function metal and form the metal gate. However, it's well known that the metal CMP itself is incapable of controlling the performance at bevel area. Even worse, coupled with the instability of CMP residua, the non-optimized litho EBR process and the side-effect of integraton scheme, this poses the challenges for peeling defect control for the sake of the potential stress mismatch, the complex film stack at boundary and the weak adhesion among different film remainings at bevel area. This works aims to come up with one overall solution to post contact glue layer peeling issue including both dielectric film peeling and metallic film peeling at wafer edge area. Besides the selection of insert point and the selectivity optimzation for bevel etch, the adjustment of substrate, litho EBR and the control range of bevel etch are also proven imperative. The final over-all solution demonstrates both kinds of peeling defects could be remarkably alleviated, thus leading to yield enhancement.