ECO Timing Optimization Using Spare Cells and Technology Remapping

Redundant-wires-aware ECO timing and mask cost optimization

“…In the spare-cell selection stage, we first identify the timing paths violating the timing constraints, which are defined as ECO paths [2].…”

“…To fix the timing violation, we may try to insert g S 2 in an adjacent net, and replace g E 1 with the adjacent spare cell g S 1 , as illustrated in Fig. 2 To identify gate sizing and buffer insertion candidates for ECO paths, we use the same timing model and bonding polygon technique as in [2] to select spare cells only in the valid region of a gate and prune other spare cells outside the bonding box. Another observation presented in [2] is the shielding effect.…”

“…2 To identify gate sizing and buffer insertion candidates for ECO paths, we use the same timing model and bonding polygon technique as in [2] to select spare cells only in the valid region of a gate and prune other spare cells outside the bonding box. Another observation presented in [2] is the shielding effect. Shielding effect states that sizing a gate g(i) and inserting a buffer substantially affect the delays of its fan-in and fan-out gates.…”

“…On an ECO path, we use the same timing model and the same bounding polygon technique in [2] to select spare-cell candidates for each gate. Unlike the work [2] that handle ECO paths sequentially, we perform ECO timing optimization on related ECO paths simultaneously by grouping ECO paths according to their spare-cell candidates.…”

“…After selecting spare cells to fix timing violations, spare-cell rewiring (ECO routing) is performed to complete the optimization. To perform gate sizing and buffer insertion using spare cells, Chen et al proposed a timing optimization flow based on dynamic programming [2]. Later, Lu et al utilized buffer insertion to resolve timing violations under input-slew and output-loading constraints [9].…”