Redundant-wires-aware ECO timing and mask cost optimization

Abstract

Spare cells are often used in engineering change order (ECO) timing optimization. By applying spare-cell rewiring techniques, timing-violated paths in a design can be fixed. In addition, mask re-spin cost economization has become a critical challenge for modern IC design, and it can be achieved by reducing the number of layers used to rewire spare cells. This paper presents the first work for the problem of ECO timing optimization considering redundant wires (unused wires or dummy metals) to minimize the number of rewiring layers. We first propose a multi-commodity flow model for the sparecell selection problem and apply integer linear programming (ILP) to simultaneously optimize all timing-violated paths. The ILP formulation minimizes the number of used spare cells and considers the routability of the selected spare cells. Then, we develop a tile-based ECO router which minimizes the number of rewiring layers by reusing redundant wires. Experimental results based on five industry benchmarks show that our algorithm not only effectively resolves timing violations but also reduces the number of rewiring layers under reasonable runtime.

A topology-based ECO routing methodology for mask cost minimization

“…To address this problem, Fang et al [5] developed a redundant-wires-aware ECO approach to improve circuit timing and reduce the number of changed masks. By reusing all unused wires and dummy metals, rewiring nets has high possibility to cross over different obstacles in a layout such that better routability is achieved and less number of changed masks is also obtained.…”

“…After selecting spare cells, simple spare-cell rewiring (i.e., ECO routing) is performed to complete ECO procedure. In order to address the routing issue, some ECO routers have been proposed [5], [8], [9]. Li et al [8] presented a tile-based ECO router to improve total wirelength and used vias.…”

“…Although many ECO optimization methodologies have been proposed in the literature [5], [8], [9], most of these works focus on how to choose desired spare cells to correct circuit functionality and to improve the circuit performance. After selecting spare cells, simple spare-cell rewiring (i.e., ECO routing) is performed to complete ECO procedure.…”

Simultaneous functional and timing ECO

“…Lu et al adopt the proper buffer type with an invariant input slew and output transition to fix timing [7]. Fang et al utilize redundant wires for routability friendliness by ILP [9]. Ho [10].…”

“…For timing ECO, prior works apply buffer insertion and gate sizing to remedy timing violations [6][7] [9]. Chen et al propose a dynamic programming based approach [6].…”