ECC Memory for Fault Tolerant RISC-V Processors

Dorflinger, Alexander; Guan, Yejun; Michalik, Sören; Michalik, Sönke; Naghmouchi, Jamin; Michalik, H.

doi:10.1007/978-3-030-52794-5_4

Cited by 8 publications

(7 citation statements)

References 6 publications

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“…The BOOM processor requires 4 additional arrays (BTB tag/data, Bi-Modal Table, and TAGE entries), resulting in a total of 9 arrays. All arrays are protected against bitflips by an ECC enhanced memory, which has been introduced in [25] and provides several configuration options (Listing 3). Parity (without correction capability but only low resource overhead), SEC, and SEC-DED are selectable as ecc_code The block_size is customizable.…”

Section: Error Correction Codes (Ecc)mentioning

confidence: 99%

A Framework for Fault Tolerance in RISC-V

Dorflinger

Kleinbeck

Albers

et al. 2022

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf

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Microcontrollers require protection against transient and permanent faults when being utilized for safetycritical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy. This work incorporates fault tolerance techniques of those domains into a framework for RISC-V processors. The implemented fault tolerance components are highly configurable to satisfy various dependability requirements. The cost of applied fault tolerance mechanisms is evaluated for both an FPGA and an ASIC implementation. Fault injection tests prove the effectiveness for error detection and cover both transient and permanent faults in logic and memories. New methods are introduced to minimize the error detection latency and achieve a reduction of up to 79%.

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Section: Error Correction Codes (Ecc)mentioning

confidence: 99%

A Framework for Fault Tolerance in RISC-V

Dorflinger

Kleinbeck

Albers

et al. 2022

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf

Self Cite

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“…However, SHAKTI-F only considers inspections in the execution stage, ignoring exceptions in other pipelines. Alexander et al [9] focused on improving the fault tolerance of the RISC-V processor in the storage architecture. They designed the ECC module based on the characteristics of the Chisel language and successfully transplanted it to the rocket and other processor cores without considering the internal core reliability.…”

Section: Related Workmentioning

confidence: 99%

“…The fault tolerance of the processor core depends on its design architecture, and commercial processor cores are often in a black box state, which makes it difficult to harden the fault tolerance [7]. The fault tolerance for storage space often uses Hamming code or ECC check technology [8,9], but Hamming code can only correct 1-bit errors, not multi-bit errors. The trigger design [10] based on Triple Modular Redundancy (TMR) technology can effectively improve fault tolerance, however, it uses many more resources.…”

Section: Introductionmentioning

confidence: 99%

“…According to the coding rules of Hamming code, the check bits are calculated as follows:𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 (3) 𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 (4) 𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 (𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 (𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 (𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 (𝑃 = 𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷 ⨁𝐷(9) …”

mentioning

confidence: 99%

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DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Shan-cong

Bao

2021

Electronics

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With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

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“…RISC-V is quickly being adopted in the space sector [8] as a replacement for the aging SPARC ISA and opens strong opportunities to develop highly reliable architectures. Recent studies [9]- [11] show that the number of fault-tolerant RISC-V cores that prevent SEUs and MBUs is still limited. While this is still true, the number of researchers and the industry that is developing fault-tolerance solutions for RISC-V is growing.…”

Section: Introductionmentioning

confidence: 99%

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Annink

Rauwerda

Hakkennes

et al. 2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

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ECC Memory for Fault Tolerant RISC-V Processors

Cited by 8 publications

References 6 publications

A Framework for Fault Tolerance in RISC-V

A Framework for Fault Tolerance in RISC-V

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

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