Early Experiences with Saving Energy in Direct Interconnection Networks

Zahn, Felix; Lammel, Steffen; Fröning, Holger

doi:10.1109/hipineb.2017.10

Cited by 11 publications

(8 citation statements)

References 15 publications

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“…Most of today's interconnection networks do not provide any mechanism for dynamic power saving suitable for HPC applications, and in particular, transition time has received little attention regarding optimizations. However, our initial results clearly show that shorter transition times increase the power saving potential significantly …”

Section: Introductionmentioning

confidence: 78%

“…Hence, the best approach to test new energy saving policies is implementing them in a hardware simulator. In our experiments, we use the existing OMNeT++‐based SAURON simulator, which is extended with several features in order to meet our demands regarding power modeling and analysis . This includes the three energy saving policies presented here, as well as instrumentation for power analysis at different levels of the network.…”

Section: Evaluation Methodologymentioning

confidence: 99%

“…The first policy we used was introduced by us in our other work. 6 The main idea of this strategy is to switch links off if they are not used, and switch them on again if data has to be transmitted. This means a switched-off link is powered up again, as soon as a packet or credit is inserted into the link's output queue.…”

Section: On/offmentioning

confidence: 99%

“…The influence of this parameter is discussed in more detailed in our other work. 6 The impact of the different policies on energy consumption and performance for the three selected workloads is shown in Figure 7. On the left side, Figure 7A depicts the execution time normalized to the execution time of a regular network without any energy saving mechanism.…”

Section: Energy Saving In Current Hardwarementioning

confidence: 99%

“…The first policy we used was introduced by us in our other work . The main idea of this strategy is to switch links off if they are not used, and switch them on again if data has to be transmitted.…”

Section: Designmentioning

confidence: 99%

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On link width scaling for energy‐proportional direct interconnection networks

Zahn

Lammel

Fröning

2018

Concurrency and Computation

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Energy consumption is one of the most important design parameters for future large-scale computing systems. While the end of Dennard scaling demands for increasing energy-proportional components, interconnection networks have not received much attention regarding this topic.However, these networks are expected to contribute about 20% to the overall power consumption of these systems in the near future. Furthermore, this fraction increases if other energy-proportional components, such as CPUs, accelerators, and memory, are not fully utilized.To avoid becoming the main contributor to power consumption and to reduce overall power consumption, it is mandatory to improve the energy-proportionality of interconnection networks. In this work, we analyze different aspects of energy-proportionality in interconnection networks for systems designed within current technical constraints but also for future systems that might be designed with different parameters. First, we discuss the impact of multiple design parameters and the most feasible approach for improved energy consumption, such as transition time and power state granularity. Based on this study, we introduce three different power saving policies, which try to address different requirements. While an on/off policy allows for large energy savings, it can also cause significant performance losses for adverse setups. In order to meet the demand for sustainable performance, we present two new policies that trade power saving potential for performance. For all three workload classes, we use a power-aware network simulation to report the impact on execution time and energy consumption compared to the current situation and an idealized network. While we show that a highly regular pattern enables power saving possibilities close to the theoretical minimum, even slight deviations from such a highly iterative and temporal behavior demand for further improvements in all policies. KEYWORDS energy-proportionality, interconnection networks, network simulation, power saving INTRODUCTIONToday's CMOS-based compute technology is mainly constrained by power consumption, as the scaling rules introduced by Dennard are no longer valid. Thus, in Post-Dennard performance scaling, traditional techniques like frequency scaling and an improved amount of instructions per cycle (IPC) are no longer applicable. Instead, scaling the amount of operations per Watt is key to performance. Due to data dependencies, data movement is an inherent part of scientific applications, and besides optimizing the amount of floating point or integer operations per Watt, the associated costs have to be considered when moving input and output operands. Furthermore, energy consumption for data movements strongly depends on distance: for short on-die links, power consumption depends linearly on the transmission distance, while for longer connections, it quickly behaves super-linear due to effects including dielectric loss and skin effect. As a result, for a clustered system, inter-node communication significantly contr...

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Section: Introductionmentioning

confidence: 78%

Section: Evaluation Methodologymentioning

confidence: 99%

Section: On/offmentioning

confidence: 99%

Section: Energy Saving In Current Hardwarementioning

confidence: 99%

Section: Designmentioning

confidence: 99%

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On link width scaling for energy‐proportional direct interconnection networks

Zahn

Lammel

Fröning

2018

Concurrency and Computation

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High-performance application mapping in network-on-chip-based multicore systems

Reza

2024

J Supercomput

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The allocation of resources and scheduling of tasks, specifically mapping, in multicore systems on-chip (MCSoC), poses significant challenges. Tasks have diverse resource requirements and interact with each other, while network-on-chip (NoC)-based MCSoC consists of heterogeneous cores and communication networks. The heterogeneity of resources in MCSoC, along with the varying computational and communication demands of applications, makes mapping a complex optimization problem. We have mathematically modeled the mapping problem in NoC-based MCSoC using mixed-integer linear programming (MILP) with the objective of minimizing the execution time of applications. This model incorporates computation and communication capacity, energy budget constraints of MCSoC, and execution time requirements of applications. We further propose heuristics, including simulated annealing (SA) and genetic algorithm (GA), considering the capacity and budget constraints of MCSoC systems to accelerate applications and provide quick mapping solutions. Simulation results demonstrate that the performance from SA and GA heuristics are very close (within 10%) to the optimal solutions from MILP across various applications for 2D-mesh NoCs with 16 to 100 cores. The energy consumption of SA and GA heuristics is also very close to the optimal solutions from MILP, with a few exceptions on small-scale 16-core NoC. Additionally, SA outperforms GA in most cases for all applications.

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