E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories

Bathen, Luis Angel D.; Dutt, Nikil

doi:10.1109/date.2011.5763191

Cited by 15 publications

(14 citation statements)

References 26 publications

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“…The more blocks to keep track the more configuration memory is necessary. One way to reduce the necessary storage would be to do first-fit allocation (e.g., continuous blocks) [7], but this may lead to fragmentation. The breakdown of the block metadata is shown in Table 2.…”

Section: Vspm Data Protectionmentioning

confidence: 99%

“…7.10, we change the architectural template from a bus-based CMP to a Network-on-Chip [9]-based Mesh architecture, which is used to evaluate different allocation policies under different circumstances: (1) Mesh size, (2) Workload size, and (3) Memory size. Figure 11 shows our experimental setup where we implemented our SPMVisor module as a SystemC TLM/CCATB [32] block and integrated it into our simulation framework [7], which interfaces with Simplescalar [3] and CACTI [39]. Table 3 shows in more detail the different parameters of our simulated architectural template.…”

Section: Experimental Goalsmentioning

confidence: 99%

“…Figure 4 shows the high-level diagram of our target platform. Our Chip-Multiprocessor (CMP) resembles the platform used in [6,7,36], which consists of a set of OpenRISC- 4 SPMVisor enhanced chip-multiprocessor like cores, distributed SPMs, an AMBA AHB [2] on-chip bus, enhanced with a secure DMA (S-DMA), and a cryptographic engine (Crypto) similar to the ones in [21,28]. The SPMVisor module behaves as an enhanced arbiter that serves requests from its masters (CPUs) to the on-chip distributed SPMs.…”

Section: Software/hardware Virtualization Support Tradeoffmentioning

confidence: 99%

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Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Bathen

Shin

Lim

et al. 2013

Des Autom Embed Syst

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Emerging multicore platforms are increasingly deploying distributed scratchpad memories to achieve lower energy and area together with higher predictability; but this requires transparent and efficient software management of these critical resources. In this paper, we introduce the concept of ScratchPad Memory virtualization, a hardware/software run-time layer (called SPMVisor) that virtualizes the scratchpad memory space in order to facilitate the use of distributed SPMs in an efficient, transparent and secure manner. We introduce the notion of virtual scratchpad memories (vSPMs), which can be dynamically created and managed as regular SPMs. The SPMVisor exploits policy-driven allocation strategies based on application privilege levels and data level prioritization metrics (e.g., utilization) to efficiently manage the on-chip memory real-estate. Our experimental results on Mediabench/CHStone benchmarks running on various Chip-Multiprocessor configurations and software stacks (RTOS, virtualization, secure execution) showed that SPMVisor enhances performance by 71 % on average and reduces power consumption by 79 % on average with respect to traditional context switching schemes. We showed the benefits of using vSPMs in a various environments (a RTOS multi-tasking environment, a virtualization environment, and a trusted execution environment). Furthermore, we explored the effects of mapping instructions and data onto vSPMs, and showed that sharing on-chip space reduces both execution time and energy by an average 16 % and 12 % respectively. We then compared our priority-driven memory allocation scheme with traditional dynamic allocation and showed an average 54 % execution time reduction and 65 % energy savings. Finally, to further validate the SPMVisor's benefits, we modified the initial bus-based architecture to include a mesh-based CMP with up to 4 × 4 nodes. We were able to observe that SPMVisor's priority-driven allocator was able to reduce execution time by an average 17 % with respect to competing allocation policies, while saving an average 65 % across various architectural configurations. We were also able to observe that SPMVisor reduces execution time by an average 12.6 % with respect to competing allocation policies, while saving an average 63.5 % in total energy for various architectural configuration running 1024 jobs.

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Section: Vspm Data Protectionmentioning

confidence: 99%

Section: Experimental Goalsmentioning

confidence: 99%

Section: Software/hardware Virtualization Support Tradeoffmentioning

confidence: 99%

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Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Bathen

Shin

Lim

et al. 2013

Des Autom Embed Syst

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“…SRAM arrays are known to have large variations which limit their minimum operating voltage and hence power. [15] achieves reliability through redundancy by optimizing RAID-like policies tuned for on-chip distributed scratchpad memories at lower power cost than ECC with voltage overscaling. Extending this, [55] allows programmers to partition their application's address space (through annotations) into virtual address regions and create mapping policies for each region depending on their requirements (fault tolerance, power, etc).…”

Section: Variability Expeditionmentioning

confidence: 99%

“…Consequently, caches are increasingly replaced by or augmented with software-controlled scratchpad memories (SPMs). The design of reliable SPMs has also received great attention recently, including efforts that address the reliability of SPMs for chip-multiprocessors (E-RoC [15] and SPMVisor [16]), or for hybrid memories (FTSPM [17]). …”

Section: Memories and Errorsmentioning

confidence: 99%

Multi-Layer Memory Resiliency

Dutt

Gupta

Nicolau

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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With memories continuing to dominate the area, power, cost and performance of a design, there is a critical need to provision reliable, high-performance memory bandwidth for emerging applications. Memories are susceptible to degradation and failures from a wide range of manufacturing, operational and environmental effects, requiring a multi-layer hardware/software approach that can tolerate, adapt and even opportunistically exploit such effects. The overall memory hierarchy is also highly vulnerable to the adverse effects of variability and operational stress. After reviewing the major memory degradation and failure modes, this paper describes the challenges for dependability across the memory hierarchy, and outlines research efforts to achieve multi-layer memory resilience using a hardware/software approach. Two specific exemplars are used to illustrate multilayer memory resilience: first we describe static and dynamic policies to achieve energy savings in caches using aggressive voltage scaling combined with disabling faulty blocks; and second we show how software characteristics can be exposed to the architecture in order to mitigate the aging of large register files in GPGPUs. These approaches can further benefit from semantic retention of application intent to enhance memory dependability across multiple abstraction levels, including applications, compilers, run-time systems, and hardware platforms.

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Lightweight Software-Defined Error Correction for Memories

Alam

Dolecek

Gupta

2020

Dependable Embedded Systems

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Reliability of the memory subsystem is a growing concern in computer architecture and system design. From on-chip embedded memories in Internet-of-Things (IoT) devices and on-chip caches to off-chip main memories, the memory subsystems have become the limiting factor in the overall reliability of computing systems. This is because they are primarily designed to maximize bit storage density; this makes memories particularly sensitive to manufacturing process variation, environmental operating conditions, and aging-induced wearout. This chapter of the book focuses on software managed techniques and novel error correction codes to opportunistically cope with memory errors whenever they occur for improved reliability at minimal cost.

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E-RoC: Embedded RAIDs-on-Chip for low power distributed dynamically managed reliable memories

Abstract: Abstract-

Cited by 15 publications

References 26 publications

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Virtualizing on-chip distributed ScratchPad memories for low power and trusted application execution

Multi-Layer Memory Resiliency

Lightweight Software-Defined Error Correction for Memories

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