E-beam shot count estimation at 32 nm HP and beyond

Choi, Jin; Lee, Sangeun; Nam, Dongseok; Kim, Byung Gook; Woo, Sang-Gyun; Cho, Han Ku

doi:10.1117/12.824284

Cited by 6 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[7][8] The shot complexity can causes the position error during the electron beam writing and as a result, the critical dimension (CD) error or pattern shift can occur. 8 Therefore, it is very important to predict the shot complexity in new device application.…”

Section: Introductionmentioning

confidence: 99%

Requirements of the e-beam shot quality for mask patterning of the sub-1X device

Park

Lee

et al. 2016

SPIE Proceedings

Self Cite

View full text Add to dashboard Cite

As the integration node becomes smaller in 193nm ArF immersion optical lithography, the complexity of optical proximity correction (OPC) has been increased continuously. Moreover, pattern design should be changed by more aggressive transformation technique such as inverse lithography technique (ILT). The greater fidelity to the target design on wafers is achieved by the application of these OPC techniques and results in the greater complexity level of the mask patterns. Complicated mask pattern consists of many corners and assist features, which raises the fraction of small shots in e-beam data. To get more accurate mask pattern, the dose stability of small shots becomes more important in a complicated mask pattern.In this paper, we present the evaluation results of the small shot handling capabilities of e-beam machines. According to the results, the information of small shots generated during data fracturing should be considered as a factor that defines the complexity of patterns in e-beam writing. It shows that the small shot printing in e-beam machines need to be improved in order to guarantee mask pattern quality.

show abstract

Section: Introductionmentioning

confidence: 99%

Requirements of the e-beam shot quality for mask patterning of the sub-1X device

Park

Lee

et al. 2016

SPIE Proceedings

Self Cite

View full text Add to dashboard Cite

show abstract

“…Currently, high-end 32 nm masks with moderate OPC can require 3 to 12 hours to write the full pattern area and complex OPC can increase this to more than 30 hours. 1 Because only a few state-of-the-art masks are required today, mask suppliers can produce these fairly easily. However, as the number of these masks rises, so will the impacts on capacity and final mask costs.…”

Section: Introductionmentioning

confidence: 99%

Fast mask writers: technology options and considerations

Litt¹,

Groves²,

Hughes³

2011

Alternative Lithographic Technologies III

View full text Add to dashboard Cite

The semiconductor industry is under constant pressure to reduce production costs even as the complexity of technology increases. Lithography represents the most expensive process due to its high capital equipment costs and the implementation of low-k1 lithographic processes, which have added to the complexity of making masks because of the greater use of optical proximity correction, pixelated masks, and double or triple patterning. Each of these mask technologies allows the production of semiconductors at future nodes while extending the utility of current immersion tools.Low-k1 patterning complexity combined with increased data due to smaller feature sizes is driving extremely long mask write times. While a majority of the industry is willing to accept times of up to 24 hours, evidence suggests that the write times for many masks at the 22 nm node and beyond will be significantly longer.It has been estimated that funding on the order of $50M to $90M for non-recurring engineering (NRE) costs will be required to develop a multiple beam mask writer system, yet the business case to recover this kind of investment is not strong. Moreover, funding such a development poses a high risk for an individual supplier. The structure of the mask fabrication marketplace separates the mask writer equipment customer (the mask supplier) from the final customer (wafer manufacturer) that will be most effected by the increase in mask cost that will result if a high speed mask writer is not available. Since no individual company will likely risk entering this market, some type of industry-wide funding model will be needed.Because SEMATECH's member companies strongly support a multi-beam technology for mask writers to reduce the write time and cost of 193 nm and EUV masks, SEMATECH plans to pursue an advanced mask writer program in 2011 and 2012.

show abstract