Step and Flash Imprint Lithography (SFIL), a form of ultraviolet nanoimprint lithography (UV-NIL), is recognized for its resolution and patterning abilities. It is one of the few next generation lithography techniques capable of meeting the resolution requirements of future semiconductor devices. However, many integration issues such as defectivity, throughput, and overlay must be resolved before SFIL can be used for semiconductor high volume manufacturing (HVM). This paper discusses the current status of SFIL, including the process and templates, and shows where more industry collaboration is needed to solve the most critical issues.
The continuing demand for higher frequency microprocessors and larger memory arrays has led to decreasing device dimensions and smaller process control windows. Decreasing process control windows have created a need for higher precision metrology to maintain an acceptable precision to tolerance ratio with a reasonable sampling rate. In order to determine and reduce across chip, across wafer, and across lot linewidth variations, higher sampling is required which, in turn, demands faster move acquire measure (MAM) times to maintain throughput. Finally, the need to detect and quantify sidewall angle changes in addition to CD measurements is becoming critical. Spectroscopic Scatterometry is a metrology technique which offers the potential to meet these requirements. This work explores some of the fundamental technology concerns for implementing scatterometry in a manufacturing environment. These concerns include mark requirements and characterization necessary for library generation. Comparison of scatterometry data to in-line CD SEM, x-sectic'n SEM, and AFM results will be presented.
SEMATECH has initiated a nanoimprint program and started imaging experiments with a Molecular Imprints Imprio300 TM system at the SEMATECH facility in Albany, NY. An overview of the SEMATECH nanoimprint development program is presented as well as an assessment of nanoimprint technology strengths and weaknesses. SEMATECH plans to explore many of the critical aspects of the nanoimprint process to drive key improvements in overlay, imprint mask cleaning, and defectivity toward making nanoimprint technology a cost-effective lithography strategy for CMOS development and manufacturing applications. Results of nanoimprint overlay with a previous level exposed on a 1.35NA immersion lithography scanner show it has noticeably improved over previous results with champion data in the 18nm range. Imprint mask cleaning on an automated tool has shown no measurable degradation of critical dimension or line width roughness after ten cleaning cycles.
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