Dynamically-wiresized Elmore-based routing constructions

Hodes, Todd D.; McCoy, B.A.; Robins, Gabriel

doi:10.1109/iscas.1994.408838

Cited by 16 publications

(17 citation statements)

References 18 publications

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“…Historically, while early works wiresized mainly clock trees [37,38,83,107] and power distribution networks [33], the wiresizing of general interconnect became viable in the early 1990's [25,26,45,91] due to the confluence of VLSI scaling trends and algorithmic advances. Wiresizing considerations can be easily incorporated into all the routing constructions discussed above [62], and can even drive the routing process itself [45], as well as other layout phases higher in the design hierarchy.…”

Section: Wiresizingmentioning

confidence: 99%

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Timing-Driven Interconnect Synthesis

Hu¹,

Robins²,

Sze³

2008

Handbook of Algorithms for Physical Design Automation

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Section: Wiresizingmentioning

confidence: 99%

“…Wiresizing considerations can be easily incorporated into all the routing constructions discussed above [62], and can even drive the routing process itself [45], as well as other layout phases higher in the design hierarchy.…”

Section: Wiresizingmentioning

confidence: 99%

Timing-Driven Interconnect Synthesis

Hu¹,

Robins²,

Sze³

2008

Handbook of Algorithms for Physical Design Automation

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“…In the case of Steiner tree construction followed by buer insertion and wire sizing, a Steiner tree optimized for delay does not necessarily result in a minimum-delay wire-sized buered Steiner tree. Recently, [7,11,14] explored the possibility of combining these steps. A simple greedy algorithm was used in [7] for tree construction with wire sizing.…”

Section: Introductionmentioning

confidence: 99%

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Okamoto¹,

Cong²

Proceedings of International Conference on Computer Aided Design

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This paper presents an ecient algorithm for buered Steiner tree c onstruction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm nds a Steiner tree with buer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree c onstruction, buer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree c onstruction and dynamic programming based buer insertion and wire sizing, while tree c onstruction and the other delay minimization techniques were c arried out independently in the past. Experimental results show the eectiveness of our approach.

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“…From (8) and (9), the short-circuit power of the load inverter can be expressed in terms of the design parameters to obtain an analytic solution for the optimum width so as to minimize power.…”

Section: B Minimizing the Transient Powermentioning

confidence: 99%

“…Furthermore, for each linewidth, a minimum transient power dissipation also exists at a specific driver size. A global minimum for the transient power is obtained by simultaneously solving (8) and (9) to determine the optimum value for each design variable. For the example circuit shown in Fig.…”

Section: B Minimizing the Transient Powermentioning

confidence: 99%

Power characteristics of inductive interconnect

El-Moursy

Friedman

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003

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Abstract-The width of an interconnect line affects the total power consumed by a circuit. The effect of wire sizing on the power characteristics of an inductive interconnect line is presented in this paper. The matching condition between the driver and the load affects the power consumption since the short-circuit power dissipation may decrease and the dynamic power will increase with wider lines. A tradeoff, therefore, exists between short-circuit and dynamic power in inductive interconnects. The short-circuit power increases with wider linewidths only if the line is underdriven. The power characteristics of inductive interconnects therefore may have a great influence on wire sizing optimization techniques. An analytic solution of the transition time of a signal propagating along an inductive interconnect with an error of less than 15% is presented. The solution is useful in wire sizing synthesis techniques to decrease the overall power dissipation. The optimum linewidth that minimizes the total transient power dissipation is determined. An analytic solution for the optimum width with an error of less than 6% is presented. For a specific set of line parameters and resistivities, a reduction in power approaching 80% is achieved as compared to the minimum wire width. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined.Index Terms-Characteristic impedance, dynamic power, inductive interconnect, short-circuit power, transient power dissipation, underdamped systems.

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Dynamically-wiresized Elmore-based routing constructions

Cited by 16 publications

References 18 publications

Timing-Driven Interconnect Synthesis

Timing-Driven Interconnect Synthesis

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Power characteristics of inductive interconnect

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