Dynamic time-slot allocation for QoS enabled networks on chip

Marescaux, Théodore; Bricke, B.; Debacker, Peter; Nollet, V.; Corporaal, Henk

doi:10.1109/estmed.2005.1518069

Cited by 28 publications

(21 citation statements)

References 8 publications

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“…Figure 7 depicts a comparison of our solution with the classic single-path solution from the AEthereal tool flow on a network with 8-by-8 mesh topology. In this setting, the multi-path approach produces a solution with more than twice the bandwidth of the single-path Although the common approach is to perform the allocation at design time, other authors have shown in [31] that it is also feasible to compute the allocation at run-time, directly on the embedded device. In order to perform allocation at run-time it is important to have an computationally efficient, low-cost allocation algorithm.…”

Section: Resultsmentioning

confidence: 99%

Multi-path routing in time-division-multiplexed networks on chip

Stefan

Goossens

2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-The exponential increase in transistor count due to technological progress has resulted in an increase in complexity and processing power of on-chip elements. Recently a stage has been reached where it is not practical anymore to increase the core size, and as a consequence the number of cores, processing elements or peripherals is being increased instead. In this study we focus on improving the efficiency of a network between those processing elements using alternative routing strategies. We focus on a multi-path slot allocation method in networks with static resource reservations, in particular networks on chip (NoC) employing time-division multiplexing (TDM). The simplicity of these networks makes it possible to implement this routing scheme without significant hardware overhead. Our proposed method, although displaying large variations between test cases, provides significant overall gains in terms of allocated bandwidth, with an average gain across all tests of 29% against an exhaustive search of single-path routes, and gains of 47% when compared to other single-path routing algorithms.

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Section: Resultsmentioning

confidence: 99%

Multi-path routing in time-division-multiplexed networks on chip

Stefan

Goossens

2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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“…Besides other proposals [17,19,20], Nostrum [16] and AEthereal [18] use synchronous TDM to provide QoS. None of these designs referred above supports different GS service levels regarding throughput and latency.…”

Section: Related Workmentioning

confidence: 91%

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Heisswolf

König

Kupper

et al. 2013

Computers & Electrical Engineering

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“…In [22], a run time slot allocation algorithm for multimedia applications is proposed that uses a depth first search to find single-slot paths. Simplicity of the algorithm makes it suitable for run time usage; but it does not necessarily find a minimum length path between the circuit end-point nodes.…”

Section: Related Workmentioning

confidence: 99%

Integrated circuit-packet switching NoC with efficient circuit setup mechanism

2014

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Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet-switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.

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Dynamic time-slot allocation for QoS enabled networks on chip

Cited by 28 publications

References 8 publications

Multi-path routing in time-division-multiplexed networks on chip

Multi-path routing in time-division-multiplexed networks on chip

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

Integrated circuit-packet switching NoC with efficient circuit setup mechanism

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