Dynamic template generation for resource sharing in control and data flow graphs

Zaretsky, David; Mittal, Gaurav; Dick, Robert P.; Banerjee, P.

doi:10.1109/vlsid.2006.75

Cited by 8 publications

(2 citation statements)

References 17 publications

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“…Zaretsky et al present an algorithm for dynamically generating templates of re-occuring patterns for resource sharing in CDFGs [21], and Martinez and Kuchcinski present a constraint-solving approach based on graph-matching to implement resource sharing in CDFGs [12].…”

Section: Related Workmentioning

confidence: 99%

Resource Sharing in Custom Instruction Set Extensions

Zuluaga

Topham

2008

2008 Symposium on Application Specific Processors

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Abstract-Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can reduce significantly the die area and energy consumption of a customized processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar sub-graph. This coupling of multiple sub-graphs, if performed naively, can increase the latency of the extension instructions considerably. And yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with only modest increases in average latency for extension instructions.Based on existing resource-sharing techniques, this study presents a new heuristic that controls the degree of resource sharing between a given set of custom instructions.Our main contributions are the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous trade-offs between die area and latency to be found and exploited.

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Section: Related Workmentioning

confidence: 99%

Resource Sharing in Custom Instruction Set Extensions

Zuluaga

Topham

2008

2008 Symposium on Application Specific Processors

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“…The heuristics do not ensure that all relevant patterns are detected. In [48] the DFG is searched step-wise and a string representation similar to a canonical form is used to substitute the subgraph isomorphism test. Only fragments with one root node can be found, so also this algorithm may miss frequent fragments.…”

Section: Related Workmentioning

confidence: 99%