Dynamic Self-Regulated Charge Pump With Improved Immunity to PVT Variations

Bou-Sleiman, Sleiman; Ismail, Mohammed

doi:10.1109/tvlsi.2013.2278375

Cited by 15 publications

(4 citation statements)

References 10 publications

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“…This is as a result of the implementation of a Colpitts voltage‐controlled oscillator [10] in the system. This ringing is thought to be caused by a single‐ended current‐steering amplifier VCO in a phase‐locked loop frequency synthesiser (also known as a PLL frequency synthesiser) [11], which reduces noise and power consumption. However, this amplifier is incapable of regulating the current mismatch in the high‐frequency band.…”

Section: Related Workmentioning

confidence: 99%

Design of a high‐performance advanced phase locked loop with high stability external loop filter

Kasilingam

Balaiyah

Nuagah

et al. 2022

IET Circuits, Devices & Syst

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For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage‐controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase‐frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage‐controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed‐forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide‐by‐47 and divide‐by‐48) that lacks a few extra flip‐flops which save considerable power and improves the frequency difficulties of the multi‐band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1‐μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS‐based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

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Section: Related Workmentioning

confidence: 99%

Design of a high‐performance advanced phase locked loop with high stability external loop filter

Kasilingam

Balaiyah

Nuagah

et al. 2022

IET Circuits, Devices & Syst

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“…These non‐idealities include CP current mismatch, PFD to CP propagation mismatch, PFD dead zone and CP charge injection – clock feedthrough. CP current mismatch is reduced by using high‐gain error amplifiers in feedback [15, 16], matching using quantised currents through successive approximation logic [17], dynamic current matching [12, 18] etc. The error amplifier‐based current matching architectures are widely implemented in PLLs with low reference frequencies due to the simplicity of the topologies.…”

Section: Proposed Mfpll For Spur Reductionmentioning

confidence: 99%

Spur reduction architecture for multiphase fractional PLLs

Biswas

Bhattacharyya

2019

IET Circuits, Devices & Systems

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In this study, a multiphase fractional phase-locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non-idealities of the phase-frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non-idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from −36 to −66 dBc through phase correction and control voltage filtering.

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“…As the output voltage changes within the working range (from 0.45 V to 0.55 V at the 0.5 V comparator reference voltage in this context), the charging/discharging current varies slightly due to the channellength modulation. To improve the current matching, Bou-Sleiman and Ismail [33] overview two main ways: forcing the current match or compensating for the current mismatch. It uses a local feedback and a replica CP to force the current match.…”

Section: A Charge-pump Nonlinearitymentioning

confidence: 99%

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math> </inline-formula> Loop

Chen

Huang

Chen

et al. 2018

IEEE Trans. Circuits Syst. I

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To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A system self-calibration algorithm is proposed to calibrate nonlinearities of the analog circuitry. The operation is robust over PVT variations since the delay information is normalized to the input clock period. To verify the proposed idea, two different digital-to-time converters performing the on-chip delay are measured and analyzed at 50-MHz clocking frequency with 0.65-ps standard time deviation per measurement. Index Terms-Digital-to-time converter (DTC), time-to-digital converter (TDC), buit-in selft-test (BIST), first-order delta-sigma modulator, noise shaping, self calibration, PLL.

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Dynamic Self-Regulated Charge Pump With Improved Immunity to PVT Variations

Cited by 15 publications

References 10 publications

Design of a high‐performance advanced phase locked loop with high stability external loop filter

Design of a high‐performance advanced phase locked loop with high stability external loop filter

Spur reduction architecture for multiphase fractional PLLs

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math> </inline-formula> Loop

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