Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs

Hecht, Ronald; Kubisch, S.; Herrholtz, A.; Timmermann, Dirk

doi:10.1109/fpl.2005.1515777

Cited by 26 publications

(7 citation statements)

References 2 publications

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“…In [16], a FPGA architecture adopting a hardwired NoC as interconnection medium is discussed. The system proposed is implemented on top of the communication infrastructure, providing a cost-efficient statically and dynamically reconfigurable architectural solution.…”

Section: Related Workmentioning

confidence: 99%

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Fiorin

Luković

Palermo³

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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Section: Related Workmentioning

confidence: 99%

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Fiorin

Luković

Palermo³

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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“…Unfortunately, NoCs have the drawback of utilizing a distinct portion of the FPGA's valuable logic resources. As outlined in [25], hardwired general purpose NoCs on FPGAs seem to be a valid approach to benefit from the best of both worlds. Regarding the current development of platform FPGAs, one has only to continue this evolution.…”

Section: Simulationmentioning

confidence: 98%

Mapping a Pipelined Data Path onto a Network-on-Chip

Kubisch

Cornelius

Hecht

et al. 2007

2007 International Symposium on Industrial Embedded Systems

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During the last years, Networks-on-Chip (NoCs) have become a true alternative for the design of complex integrated Systems-on-Chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and Quality-of-Service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design paradigms actually tip the scales for the chosen application domain. In this paper, we discuss the level of QoS needed in a specific NoC for a packet processing application. This is done in the light of preliminary investigations for the redesign of an existing packet processing system because that system's current architecture exhibits drawbacks regarding performance and further scalability. Therefore, we considered to take advantage of an NoC communication architecture. A simple NoC was developed, which knowingly omits sophisticated QoS mechanisms. Relying on the lessons, which have learned from the history and development of the Internet, we argue that a simple and plain NoC suffices for applications as the one discussed.

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“…With the increase of available reprogrammable logic cells, following works explored the possibility to implement an entire NoC-based MPSoC on FPGA [1], [2].…”

Section: Related Workmentioning

confidence: 99%

Stack protection unit as a step towards securing MPSoCs

Luković

Pezzino

Fiorin

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Reconfigurable technologies are getting popular as an instrument not only for verification and prototyping but also for commercial implementation of Multi-Processor Systemon-Chip (MPSoC) architectures. These systems, in particular Network-on-Chip (NoC) based ones, have emerged as a design strategy to cope with increased requirements and complexity of modern applications. However, the increasing heterogeneity, coupled with possibility of reconfiguration, makes security become one of major concerns in MPSoC design. In this work, we show a solution for FPGA based designs against one of the most widespread types of attacks -code injection. Our response to tackle this challenge is given in form of Stack Protection Unit (SPU) embedded into processing cores. MicroBlaze soft-core processor serves as a case study for verification of the proposed solution in FPGA technology.

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Dynamic reconfiguration with hardwired networks-on-chip on future FPGAs

Cited by 26 publications

References 2 publications

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Mapping a Pipelined Data Path onto a Network-on-Chip

Stack protection unit as a step towards securing MPSoCs

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