Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System

Abstract

Partial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design.

FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

“…Finally, in order to acquire their hardware cost for the different modules of our QPSK ADCRL based on FPGA, the FPGA synthesis tool, ISE Design Suite 12.2, from FPGA vendor Xilinx is used, and its chip of Virtex5 family, XC5VLX50, which supports dynamic reconfiguration technology seen as a core technology to implement SDR [25] on FPGA is selected. The synthesis results are given in Table 3.…”

Partially reconfigurable TVWS transceiver for use in UK and US markets

“…This technique lends itself well to the concept of software deÞned radio, enabling a single FPGA device to support a multitude of radio functionalities while sharing the same hardware resources [13]. This can be achieved by dynamically altering the functionality of the device by downloading partial bitstream Þles from external memory [14], [15].…”

“…Each RP has the ability for the logic to be swapped, thus changing the functionality, using PR while the remainder of the device continues its operation [13]. A ReconÞgurable Module (RM) is the swappable logic that is associated with the RP.…”

“…The implementation of PR does not enable the clock frequency to be dynamically changed as the Digital Clock Manager (DCM) that is used to synthesise the clock must be implemented in static logic [13]. Therefore, PR alone is not sufÞcient for the implementation of the reconÞgurable transceiver system.…”

Adaptive reconfigurable V-BLAST type equalizer for cognitive MIMO-OFDM radios

“…The concept of software radio on the other hand relies on the development of DSP technology, that is flexible, reconfigurable, and reprogrammable by software to adapt to an environment where there are multiple services, standards, and frequency bands [11]. Correspondingly, the infrastructure in a software radio system is generally required to use reconfigurable VLSI hardware components such as DSP chip sets [12], FPGAs [13], embedded processors [14], and even general purpose processors [15].…”