Dynamic operand transformation for low-power multiplier-accumulator design

Fujino, Masahiro; Moshnyaga, Vasily G.

doi:10.1109/iscas.2003.1206276

Cited by 11 publications

(2 citation statements)

References 14 publications

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“…If the data with smaller effective dynamic range is Booth coded, then the partial products have greater chance to be zero and decreases the switching activities of partial products. Fujino and Moshnyaga (2003) proposed a multiply accumulate design using dynamic operand transformation technique in which current values of the input are compared with previous values (Fujino and Moshnyaga, 2003). If more than half of the bits in an operand change, then it is dynamically transformed to its two's complement in order to decrease the transition activity during multiplication.…”

Section: Related Researchmentioning

confidence: 99%

Low Power Multiplier by Effective Capacitance Reduction

Peddamgari¹,

Radhakrishnan²

2017

American Journal of Engineering and Applied Sciences

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In this study we present an energy efficient multiplier design based on effective capacitance minimization. Only the partial product reduction stage in the multiplier is considered in this research. The effective capacitance at a node is defined as the product of capacitance and switching activity at that node. Hence to minimize the effective capacitance, we decided to ensure that the switching activity of nodes with higher capacitance is kept to a minimum. This is achieved by wiring the higher switching activity signals to nodes with lower capacitance and vice versa, for the 4:2 compressor and adder cells. This reduced the overall switching capacitance, thereby reducing the total power consumption of the multiplier. Power analysis was done by synthesizing our design on Spartan-3E FPGA. The dynamic power for our 16×16 multiplier was measured as 360.74 mW and the total power 443.31 mW. This is 17.4% less compared to the most recent design. Also, we noticed that our design has the lowest power-delay product compared to the multipliers presented in literature.

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Section: Related Researchmentioning

confidence: 99%

Low Power Multiplier by Effective Capacitance Reduction

Peddamgari¹,

Radhakrishnan²

2017

American Journal of Engineering and Applied Sciences

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“…Alternatively, the optimized circuits presented in [7] and [16] demonstrate more balanced data paths and an efficient partial-product array structure that outperform other higher level implementations. Row and column bypassing [30], [31], dynamic operand interchanges [32], [33] were also considered to exploit the multiplier input asymmetry for low power. These techniques are questionable in general cases as the extra circuit overhead is a heavy burden.…”

Section: Introductionmentioning

confidence: 99%

Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

Ranasinghe

Gerez

2020

IEEE Trans. VLSI Syst.

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This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.

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Low Power Optimized Array Multiplier with Reduced Area

Devi

Singh

2011

High Performance Architecture and Grid Computing

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Dynamic operand transformation for low-power multiplier-accumulator design

Cited by 11 publications

References 14 publications

Low Power Multiplier by Effective Capacitance Reduction

Low Power Multiplier by Effective Capacitance Reduction

Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

Low Power Optimized Array Multiplier with Reduced Area

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