Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers

Abstract

This article presents a novel implementation scheme of the essential circuit blocks for high-performance, full-precision Booth multipliers leveraging a hybrid logic style. By exploiting the behavior of parasitic capacitance of MOSFETs, a carefully engineered design style is employed to reduce dynamic power dissipation while improving the glitch immunity of the circuit blocks. The circuit-level techniques along with the proposed signal-flow optimization scheme prevent the generation and propagation of spurious activities in both partial-product and adder-tree stages. Two full-precision Booth multipliers built from proposed strategies were compared to the state-of-the-art versions known from literature by means of extensive post-layout simulations in 65-nm CMOS technology. The proposed versions on average demonstrated up to 10% and 30% power savings in general.

Novel Ultra-Low-Voltage Flip-Flops: Near-Vth Modeling and VLSI Integration

“…1(b)) between the capturing latch and the output MUX as well as between node N and L. Steeper clock transitions can alleviate this failure. However, this eventually increases the gate parasitics [16] of the local clock buffers and therefore the clock tree power.…”

“…The improvement to these specifications is only restricted by the M4-M9 device sizing requirement stated in Section III-A. With the aid of parasitic modeling [16], the decomposed setup and hold paths of both circuits are depicted in Fig. 3(d).…”

“…Here, the charging and the discharging times of node SP through the given paths are considered as the minimum time delays for the D input to become stable and for M6 to properly latch the LKP value. R D , C d/s represent the drain resistance and the parasitic capacitances (off/on state) of the MOSFETs respectively [16]. With the aid of the modeling scheme presented in [16], the minimum setup/hold requirements can be written as follows:…”

“…R D , C d/s represent the drain resistance and the parasitic capacitances (off/on state) of the MOSFETs respectively [16]. With the aid of the modeling scheme presented in [16], the minimum setup/hold requirements can be written as follows:…”

“…Besides, the selection of a proper input stimuli for characterization plays a vital role at near-V th levels. Therefore some alternative measurement schemes and the near-V th parasitic modeling [16]- [18] will be studied in this paper.…”