Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking

Tida, Umamaheswara Rao; Zhuo, Cheng; Liu, Leibo; Shi, Yiyu

doi:10.1109/tcad.2018.2887053

Cited by 17 publications

(11 citation statements)

References 28 publications

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“…Recently TSV-inductor has been proposed to overcome this metal resource consumption of a planar spiral inductor by utilizing dummy TSVs to form an on-chip vertical structure for 2.5D/3D designs [15]. Such a structure enables more compact designs with smaller parasitics and can be applied to low frequency applications up to several hundreds of mega-hertz [9][10][11][12][13][14].…”

Section: Tsv-inductormentioning

confidence: 99%

“…Recently, with the advancement of 3D integration technology, a through-silicon-via (TSV) based on-chip inductor was introduced in [7][8][9][10][11][12][13][14]. It was found that a toroidal TSV-inductor, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

“…The electrical properties impact and its reliability is discussed in [9] and TSV inductor application toward multi-tier regulation is discussed in [38,39]. Other applications such as resonant clocking [12] and RF circuits [13] are implemented using TSV inductors, with the physics-based modeling approach detailed in [12]. To improve its inductance and quality factor, a magnetic core can be inserted into the structure to achieve high quality factor and L/Rdc [6,7,[16][17][18][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

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Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Wen

Xiao

Chen

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many on-chip applications. Recently through-silicon-via (TSV) based inductor (also known as TSV-inductor) with a magnetic core has been proved to be a viable option for the on-chip DC-DC converter. The operating conditions of these inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, there is a critical need to study the design and optimization details of magnetic core TSV-inductors with the unique 3D structure embedding magnetic core. This paper aims to provide a clear understanding of the modeling details of a magnetic core TSV-inductor and a design and optimization methodology to assist efficient inductor design. Moreover, a machine learning assisted model combining physical details and artificial neural network (ANN) is also proposed to extract the equivalent circuit to further facilitate DC-DC converter design. Experimental results show that the optimized TSV-inductor with the magnetic core and air-gap can achieve inductance density improvement of up to 7.7 × and quality factor improvements of up to 1.6 × for the same footprint compared with the TSV-inductor without a magnetic core. For on-chip DC-DC converter applications, the converter efficiency can be improved by up to 15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.

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Section: Tsv-inductormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Wen

Xiao

Chen

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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“…Replacing conventional inductor and capacitor to TSV based structures achieves a 2.2× and 16.3× reduction in area, respectively. A new scheme to use idle TSVs to form inductors in LC resonant clock for 3D ICs to reduce the power consumption in the CDN was proposed in (36) . Experimental results on industrial designs show that the power consumption is reduced by up to 47.9% compared to square-wave conventional CDNs.…”

Section: Introductionmentioning

confidence: 99%

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Esmaeili¹,

Imdoukh²

2021

IJST

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“…With the continuous scaling and growing power density, power management has been a concerning topic for microprocessors to achieve good energy efficiency [1][2][3]. This is especially critical for battery-powered mobile devices, which are featured with frequent power state transition and management for varying workloads [4,5]. While such management and transition can be achieved through cooling and shutting down part of circuitry, dynamic voltage and frequency scaling (DVFS) is probably the most commonly used technique to enable energy efficiency [2,3].…”

Section: Introductionmentioning

confidence: 99%

An Efficient and Flexible Learning Framework for Dynamic Power and Thermal Co-Management

Cao

Shen

Zhang

et al. 2020

Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD

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At the era of Artificial Intelligence and Internet of Things (AIoT), battery-powered mobile devices are required to perform more sophisticated tasks featured with fast varying workloads and constrained power supply, demanding more efficient run-time power management. In this paper, we propose a deep reinforcement learning framework for dynamic power and thermal co-management. We build several machine learning models that incorporate the physical details for an ARM Cortex-A72, with on average 3% and 1% error for power and temperature predictions, respectively. We then build an efficient deep reinforcement learning control incorporating the machine learning models and facilitating the run-time dynamic voltage and frequency scaling (DVFS) strategy selection based on the predicted power, workloads and temperature. We evaluate our proposed framework, and compare the performance with existing management methods. The results suggest that our proposed framework can achieve 6.8% performance improvement compared with other alternatives. CCS CONCEPTS • Computing methodologies → Modeling and simulation; • Hardware → Chip-level power issues; • Computer systems organization → Embedded systems.

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Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking

Cited by 17 publications

References 28 publications

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

An Efficient and Flexible Learning Framework for Dynamic Power and Thermal Co-Management

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