Dynamic Fault Imaging of VLSI Random Logic Devices

May, T.C.; Scott, Guy L.; Meieran, Eugene S.; Winer, Paul; Rao, Valluri

doi:10.1109/irps.1984.362025

Cited by 42 publications

(6 citation statements)

References 9 publications

(10 reference statements)

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“…In 1984, May and his coauthors from Intel were awarded "Best Paper" at the International Reliability Physics Symposium for a very revealing single-event experiment on an Intel microprocessorunderdynamicoperation [13]. Usinganexperimentaltechnique of dynamic fault imaging, May demonstrated the temporal progression of a single-event disturbance from a local perturbation to a massive fault condition encompassing most of the microprocessor circuitry.…”

Section: See: a Brief Historymentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

894

427

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Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

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Section: See: a Brief Historymentioning

confidence: 99%

Basic mechanisms and modeling of single-event upset in digital microelectronics

Dodd

Massengill

2003

IEEE Trans. Nucl. Sci.

894

427

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“…The most notable of these involve image subtraction done in an analog, pixel-by-pixel manner or in a digital, frame-by-frame manner. Frameby-frame techniques [10,11,12] have been used to subtract an image of a passing IC from a corresponding image of a failing IC. Nodes not associated with the failure, i.e.…”

mentioning

confidence: 99%

Fault Contrast: A New Voltage Contrast VLSI Diagnosis Technique

Stivers

Ferguson

1986

24th International Reliability Physics Symposium

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sorted out and discarded, the better.Fault contrast is a differential analog technique that yields high-quality voltage contrast images of integrated circuit (IC) pass vs. fail operation.Fault contrast is applicable where the IC failure mode is sensitive to an external parameter, e.g. clock frequency or supply voltage. Fault contrast requires only simple and inexpensive analog signal processing. We demonstrate fault contrast with an analysis of an Intel 80286 microprocessor failure. Introducti onA major class of IC failures are those in which the IC can be made to pass or fail by varying an external parameter, e.g. clock frequency or supply voltage. These failure modes reflect design and process marginalities that must be characterized to optimize IC performance and yield. This paper describes a combination of voltage contrast measurement and special IC test procedures that quickly finds the the origin of failures of this class. This technique, fault contrast, yields images in which failing nodes stand out against all others. Fault contrast is a purely analog technique requiring only a minor modification to a conventional stroboscopic voltage contrast scanning electron microscope (SEM).The fault contrast signal is a measure of voltage differences between sequential program executions while the IC is caused to alternately pass and fail by the variation of an external parameter. This parameter can be supply voltage, clock frequency, input voltage level, programming voltage, illumination, etc. The only limitation on the parameter is that it must be alterable with every execution of the diagnostic program.Fault contrast is therefore applicable to an extensive class of vol tage contrast applications. Fault contrast yields the results of digital frame subtraction, however, fault contrast requires only simple analog signal processing and simple logic to implement. In addition, fault contrast is immune to many artifacts that tend to complicate techniques based on digital frame subtraction.Fault contrast is a variation of voltage contrast, an electron beam probing technique that can probe internal nodes of an IC without contact, destruction, or capacitive loading. Several groups have developed and reported on voltage contrast technology [ 1 2, 3, 4, 5, 6, 7, 8, 9]. The power of voltage contrast lies in its ability to access most nodes of an IC by merely deflecting an electron beam to those nodes. SEMs can image the voltages on an IC by rastering the electron beam over a field on the IC. The imaging mode is so easy to use that large amounts of voltage data of nodes in the neighborhood of the failing nodes are usually acquired during a typical voltage contrast analysis. The acquisition of these extraneous data does have practical consequences. These extraneous data must be subsequently sorted out to reveal the failure. This can take more time than the data acquisition itself. Furthermore, the data acquisition speed itself is limited by the electron beam current, which can average as low as 1 pa in the low-duty-cycle strobos...

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“…determines the regions of logic affected by corrupted information. For example, the hit node, and other nodes in the path, may supply erroneous data to a number of other gates (this number is defined by the fan-out); a single latched error can result in multiple errors [7]. Each potential path of corrupted data to other latches must be evaluated to determine whether the logic-state environment of the destination latches supports incorporation of erroneous data.…”

Section: Seu Analysis Using Sitamentioning

confidence: 99%

“…Therefore, experimental characterizations may not simulate accurately the vulnerability of an IC running actual software. Perhaps more important, since a single error introduced into an internal latch can result in multiple output errors [7], experimental methods cannot differentiate the effects of hardware SEU vulnerability from the effects of errors propagated by a particular test-vector set.…”

Section: Introductionmentioning

confidence: 99%

Simulation of SEU transients in CMOS ICs

Kaul

Bhuva

Kerns

1991

IEEE Trans. Nucl. Sci.

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Available analytical models for the number of singleevent-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combhtional logic circuits to SEU. SITA is describcd in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that iondevice interactions produce erroneous signals capable of propagating to a latch (or an output node), and logic-level simulation to predict the spread of such emneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITA offers several factors of 10 savings in simulation time over SPICE.

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Dynamic Fault Imaging of VLSI Random Logic Devices

Abstract: A technique is described for acquiring and imaging faults in random logic devices such as microprocessors and other VLSI chips. Logic states for both faulty and

Cited by 42 publications

References 9 publications

Basic mechanisms and modeling of single-event upset in digital microelectronics

Basic mechanisms and modeling of single-event upset in digital microelectronics

Fault Contrast: A New Voltage Contrast VLSI Diagnosis Technique

Simulation of SEU transients in CMOS ICs

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