Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

Kocan, Fatih; Saab, D.G.

doi:10.1007/s10836-007-5009-3

Cited by 7 publications

(4 citation statements)

References 26 publications

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“…And the total reliability of QGT implementation for C17 with two output QT voters is calculated from (16) as…”

Section: Comparison With Tmrmentioning

confidence: 99%

“…Static techniques, also called as defect tolerant methods, are robust, non-adaptive in nature and effectively mask both permanent and transient types of faults. All modules including the redundant spares are active and powered on simultaneously in case of static approaches [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] whereas in dynamic recovery technique (also known as defect avoidance method), spare modules are activated only upon identification of failure of currently active modules, but the approach cannot recover from transient defects if not identified upon testing [16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

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Fault tolerant architecture design using quad‐gate‐transistor redundancy

Mukherjee¹,

Dhar²

2015

IET Circuits, Devices & Systems

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In the current era of speed and recent trend of device miniaturisation, failure rates have been increased with the increase in the design complexity and the density of transistors in chip and hence reliability issues at circuit level have become more prominent and challenging. In this study, the authors propose a new static fault tolerant method called quad-gate-transistor, which uses quadded-transistor output logic with gate level quad implementation of the given circuitry to make the system defect tolerant. Such combination of gate and transistor level redundancy provides significantly higher reliability over classical triple modular redundancy and other existing static approaches as supported by extensive simulation results using some of the ISCAS 85 benchmark and other standard circuits. The proposed method also takes care of most of the limitations that restrict the use of the existing static methods in practical applications.

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“…And the total reliability of QGT implementation for C17 with two output QT voters is calculated from (16) as…”

Section: Comparison With Tmrmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fault tolerant architecture design using quad‐gate‐transistor redundancy

Mukherjee¹,

Dhar²

2015

IET Circuits, Devices & Systems

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“…Moreover, many of statistical researches proved this statement [15,16].Combinational circuits occupy a considerable portion of processing chips in comparison with sequential circuits. For example in FPGAs,The ratio of using combinational circuits to sequential ones varies between 5 to 100 times [17,18]. Fig.1: Overall new approach framework Continuous device scaling,higher degree of pipeliningand decreasing electrical masking effect, contribute to the increase in soft error rates in combinational circuits [10].Transient faults in combinational circuits are catching up with errors in memory elements [3].…”

Section: Introductionmentioning

confidence: 99%

A Fault Detection Method for Combinational Circuits

Zoraghchian

Didehban

Mehrabian

2016

International Journal of Advanced Network, Monitoring and Controls

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As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more vulnerable to permanent and transient hardware faults. Most microprocessor designers focus on protecting memory elements among other parts of microprocessors against hardware faults through adding redundant error-correcting bits such as parity bits. How ever, the rate of soft errors in combinational parts of microprocessors is consider edas important as in sequential parts such as memory elements nowadays. The reason is that advances in scaling technology have led to reduced electrical masking .This paper proposes and evaluates a logic level fault-tolerant method based on parity for designing combinational circuits. Experimental results on a full adder circuit show that the proposed method makes the circuit fault-tolerant with less overhead in comparison with traditional methods. It will also be demonstrated that our proposed method enables the traditional TMR method to detect multiple faults in addition to single fault masking.

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“…At the same time, fault emulation approaches in hardware have included vector processors [12], [13], multi-processors, Graphics Processing units [14], supercomputers [15] as well as reconfigurable computing platforms [16], [17]. These approaches have their own merit but mostly suffer from requiring significant design time and effort and require the use of complex and very expensive specialized hardware.…”

Section: Introductionmentioning

confidence: 99%

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults

Dunbar¹,

Nepal²

2011

JCP

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Abstract-This paper investigates the use of reconfigurable computing and readily available Field Programmable Gate Array (FPGA) platforms to expedite the generation of input-patterns for testing integrated circuits after manufacture. Unlike traditional fault simulation approaches, our approach emulates single stuckat fault behavior in a circuit and finds the minimum test pattern set to detect it. In this paper, we present a method to insert faults into a circuit netlist by identifying circuit fault sites. We then present our parallel method of fault emulation and describe our method to organize and compress the input patterns needed to identify all faults. Using circuits from the ISCAS and MCNC benchmark suites, we show that our approach does better than a commercial tool in test-set reduction.

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Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

Cited by 7 publications

References 26 publications

Fault tolerant architecture design using quad‐gate‐transistor redundancy

Fault tolerant architecture design using quad‐gate‐transistor redundancy

A Fault Detection Method for Combinational Circuits

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults

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