Fault tolerant architecture design using quad‐gate‐transistor redundancy

Abstract

In the current era of speed and recent trend of device miniaturisation, failure rates have been increased with the increase in the design complexity and the density of transistors in chip and hence reliability issues at circuit level have become more prominent and challenging. In this study, the authors propose a new static fault tolerant method called quad-gate-transistor, which uses quadded-transistor output logic with gate level quad implementation of the given circuitry to make the system defect tolerant. Such combination of gate and transistor level redundancy provides significantly higher reliability over classical triple modular redundancy and other existing static approaches as supported by extensive simulation results using some of the ISCAS 85 benchmark and other standard circuits. The proposed method also takes care of most of the limitations that restrict the use of the existing static methods in practical applications.