Dynamic and adaptive SPM management for a multi-task environment

Ji, Weixing; Deng, Ning; Shi, Feng; Zuo, Qiting; Li, Jiaxin

doi:10.1016/j.sysarc.2010.11.002

Cited by 10 publications

(8 citation statements)

References 15 publications

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“…4) Extensive experiments were conducted to compare the energy delay product (EDP) of various on-chip memory architectures. The proposed method can decrease the EDP by 35% to 53% when compared to a cache-only on-chip memory architecture, and 19% to 31% when compared to a previous paper [6] for various cache sizes and associativities. The rest of this paper is organized as follows.…”

Section: Introductionmentioning

confidence: 82%

“…Since many embedded applications are executed in open environments, in which the SPM information may vary, the information is usually unknown during the compilation of applications. Methods that consider runtime data access behavior for SPM allocation have been proposed to improve the efficiency of SPM utilization [6], [29]. Reference [29] proposed a dynamic method that uses the location of stack pointers to determine SPM space allocation.…”

Section: B Dynamic Allocation Methodsmentioning

confidence: 99%

“…If SPM is full before the movement, the page in SPM whose address is farthest from the stack pointer is removed from SPM. Ji et al [6] proposed a memory reference sampling SPM allocation method (MRSSA). This method migrates frequently accessed pages to on-chip SPM according to a random-sampling-based scheme.…”

Section: B Dynamic Allocation Methodsmentioning

confidence: 99%

“…To further reduce the frequency of accessing off-chip memory, some studies [4]- [6] added a mini-cache in the SPM architecture between the processor and DRAM, as shown in Fig. 1(e), where the access energy consumption of the minicache is smaller than that of SPM.…”

Section: Introductionmentioning

confidence: 99%

“…Many papers have focused on improving SPM utilization or reducing off-chip memory access in hybrid on-chip memory architectures by moving frequently accessed data into on-chip SPM [4]- [6]. However, such approaches may not effectively reduce the number of off-chip memory accesses due to the following reasons.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management

Chang¹,

Lin²,

Chien³

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Scratchpad memory (SPM) has been increasingly used in embedded systems due to its higher efficiency in terms of energy and area compared to that of ordinary cache. A hybrid onchip memory architecture that combines SPM with a mini-cache has been proposed. One key issue for hybrid on-chip memory architectures is to reduce the number of off-chip memory accesses and energy consumption. Existing methods achieve this by moving the most frequently accessed data into SPM. However, these methods may be ineffective because the main source of off-chip memory accesses may not be the most frequently accessed data. Instead, most off-chip memory accesses are caused by cache misses, so reducing the latter will reduce the former. Cache misses are mainly caused by data contending for cache lines. Therefore, this paper proposes a contention-aware SPM allocation method for hybrid on-chip management. The number of cache misses for a page is used as a metric to determine whether a page should be moved to SPM. When the number of misses for a page exceeds a threshold, the page is moved to SPM, reducing cache contention. Experimental results show that the proposed method can reduce the energy delay product by 35% to 53% compared to a cacheonly on-chip memory architecture and 19% to 31% compared to an existing hybrid on-chip memory architecture.Index Terms-Cache, energy-delay product (EDP), hybrid on-chip memory, scratchpad memory (SPM).

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Section: Introductionmentioning

confidence: 82%