A Semi-automatic Scratchpad Memory Management Framework for CMP

Deng, Ning; Ji, Weixing; Li, Jaxin; Zuo, Qiting

doi:10.1007/978-3-642-24151-2_6

Cited by 3 publications

(2 citation statements)

References 18 publications

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“…The runtime routine monitors the application behaviour and attempts to match it to one of the known profiles, and maps data to SPM accordingly to reduce energy consumption. Deng et al [60] define a framework that allows programmers to guide runtime decisions for allocating heap data to SPM in order to reduce energy consumption. Alvarez et al [61] and Komuravelli et al [62] both propose hybrid memory hierarchies (i.e.…”

Section: Spm Management For Modern Many‐core Architecturesmentioning

confidence: 99%

Automatic management of Software Programmable Memories in Many‐core Architectures

Shrivastava

Dutt

Cai

et al. 2016

IET Computers & Digital Techniques

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Software Programmable Memories, or SPMs, are raw on-chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on-chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM-based processors. Traditionally, SPMs have been utilized in embedded systems, especially multimedia and gaming systems, but recently research on SPM-based systems has seen increased interest as a means to solve the memory scaling challenges of manycore architectures. This article presents an overview of the state of the art in SPM management techniques in manycore processors, summarizes some recent research on SPM-based systems, and outlines future research directions in this field.

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Section: Spm Management For Modern Many‐core Architecturesmentioning

confidence: 99%

Automatic management of Software Programmable Memories in Many‐core Architectures

Shrivastava

Dutt

Cai

et al. 2016

IET Computers & Digital Techniques

View full text Add to dashboard Cite

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“…In some cases, the compiler can generate DMA instructions automatically [38,40]. In others, programmers must explicitly manage data movement [10,13,24,27].…”

Section: Introductionmentioning

confidence: 99%

Spx64

Singh

Dave

Zardoshti

et al. 2020

ACM Trans. Archit. Code Optim.

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General-purpose computing systems employ memory hierarchies to provide the appearance of a single large, fast, coherent memory. In special-purpose CPUs, programmers manually manage distinct, non-coherent scratchpad memories. In this article, we combine these mechanisms by adding a virtually addressed, set-associative scratchpad to a general purpose CPU. Our scratchpad exists alongside a traditional cache and is able to avoid many of the programming challenges associated with traditional scratchpads without sacrificing generality (e.g., virtualization). Furthermore, our design delivers increased security and improves performance, especially for workloads with high locality or that interact with nonvolatile memory.

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KGT: An Application Mapping Algorithm Based on Kernighan–Lin Partition and Genetic Algorithm for WK-Recursive NoC Architecture

Zhang

Wang

2021

Intelligent Computing Theories and Application

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A Semi-automatic Scratchpad Memory Management Framework for CMP

Cited by 3 publications

References 18 publications

Automatic management of Software Programmable Memories in Many‐core Architectures

Automatic management of Software Programmable Memories in Many‐core Architectures

Spx64

KGT: An Application Mapping Algorithm Based on Kernighan–Lin Partition and Genetic Algorithm for WK-Recursive NoC Architecture

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