Duty‐cycle detector based on time‐to‐digital conversion

Abstract

A duty cycle detector based on time-to-digital conversion is presented. It combines the advantages of analogue (high accuracy and simplicity) and digital (digital output) duty cycle correctors in a simple and straightforward topology. Two identical circuits detect the high and low phases of the input clock and deliver two digital words. These two words are then sufficient to accurately estimate the input duty cycle. By using the same topology for both circuits, accuracy is affected only by mismatches between them. Designed in a bulk 28nm CMOS technology the proposed duty cycle detector achieves a maximum linearity error of 4% and a resolution of 0.5% over corners and an input duty cycle range of [20, 80]%.Introduction: Microprocessors, memory interfaces and high-speed data transceivers rely on high-frequency clocks with excellent duty cycle to maximise their performance [1][2][3][4]. This is particularly important in systems where both rising and falling edges of the clock are used to execute operations [2,4].A typical clock distribution tree consists of long chains of buffers. Process variability, device mismatches and voltage domain crossing, however, cause each of these buffers to introduce a certain amount of duty cycle error. This error propagates along the clock tree, accumulates and eventually can cause severe limitation to the system performance. This is the main reason for the numerous techniques and circuits developed over the last decades to mitigate and possibly eliminate any duty cycle error the clocks might experience.Analogue-based duty cycle correctors (DCC) can be very accurate [5]. However, since they usually require analogue feedback loops, where the correcting signal is stored in a capacitance, they need the input clock to toggle continually. In other words, the clock cannot be stopped, not even temporarily; or else the duty cycle correction is compromised and the DCC needs to acquire lock again.Digital-based DCCs, on the other hand, have the capability to store the correcting signal in digital registers indefinitely. Therefore, the clock can be stopped anytime without the risk of losing the information. The digital DCCs proposed in the literature, however, are mostly based on delay line loops (DLLs). The DLL is locked to one clock period and the output clock is 'reconstructed' tapping specific phases directly from the DLL [6,7]. These circuits can be quite complex, especially if the target is a duty cycle with high resolution and accuracy. The alternative to DLLs would be expensive analogue-to-digital converters (ADCs) where the averaged voltage of the input clock would be sampled by the ADC and the binary output word used to correct the duty cycle.This Letter proposes a duty cycle detector where the widths of the clock high and low phases are converted to digital words through a time-to-digital converter. The information carried by these two digital words is then sufficient to accurately calculate the clock duty cycle. Neither DLLs nor ADCs are needed and the digital words can be readily sto...

Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators

“…Figure 5 shows an example of an on-chip duty-cycle detector that can be used for pre-bond TSV test. This is a time-to-digital converter based on the circuit proposed in [31]. The key idea of this detector is to integrate a constant current during (a) T on and (b) T off until a certain threshold voltage is reached and compare the integration times of (a) and (b).…”

“…A major difference of this duty-cycle detection method from that proposed in [31] is that we use the same circuitry for sequential measurement of n on and n off by inverting the input signal with an XOR gate. Therefore, the effect of random-process variations is virtually cancelled out.…”

“…Therefore, the effect of random-process variations is virtually cancelled out. The method proposed in [31] uses two copies of the detector, one of which has an inverter in front of Q1 to invert the signal. This allows for measurement of n on and n off in parallel; however, local mismatches between the two circuits decrease the accuracy of the detector.…”

Test and debug solutions for 3D-stacked integrated circuits

“…A major difference of this duty-cycle detection method from that proposed in [92] is that we use the same circuitry for sequential measurement of n on and n off by inverting the input signal with an XOR gate. Therefore, the effect of random-process variations is virtually cancelled out.…”

“…Therefore, the effect of random-process variations is virtually cancelled out. The method proposed in [92] uses two copies of the detector, one of which has an inverter in front of Q1 to invert the signal. This allows for measurement of n on and n off in parallel; however, local mismatches between the two circuits decrease the accuracy of the detector.…”