DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture

Kamali, Hadi Mardani; Azar, Kimia Zamiri; Hessabi, Shaahin

doi:10.1109/tc.2017.2735399

Cited by 22 publications

(4 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This tool has additional features to reconfigure the system. AdapNoC [49] and DucNoC [50] BookSim] is a standard cycle-accurate interconnection network simulator. Booksim is used to customize the router of the NoC.…”

Section: Noc Toolsmentioning

confidence: 99%

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Balamurugan¹,

Umamaheswaran

Mamo³

et al. 2022

J. Phys. Commun.

View full text Add to dashboard Cite

A few decades ago, communication inside the chip is done by transferring signals between the cores. This conventional method is not worthy because of the increase in latency and power consumption. To rectify this issue Network-on-Chip (NoC) technology has emerged. NoC technology is invented to transfer data packets instead of signals. Machine Learning NoC (M/LNoC) is a very fast-growing technology in today’s Integrated Circuit world for the communication between Intellectual property (IP) cores. The machine learning algorithms are used in the existing and emerging novel NoCs. In this paper, various evolving NoC technologies to decrease the transfer latency, power consumption of the IC is addressed for the implementation of the machine learning algorithm. The NoCs working with machine learning algorithms are called M/L NoC. We also provided the security issues to be focused- on in the M/L NoC. Also, we have provided the available NoC tools for the NoC researchers.

show abstract

Section: Noc Toolsmentioning

confidence: 99%

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Balamurugan¹,

Umamaheswaran

Mamo³

et al. 2022

J. Phys. Commun.

View full text Add to dashboard Cite

show abstract

“…It provides programmability by decoupling the simulator architecture from the architecture of the simulated on-chip network. Similarly, DuCNoC [49] maps on-chip networks to the PL of a Zynq-7000 SoC. Like HEROv2, the on-chip network is highly configurable and modeled cycle-accurately at 10 MHz and more in DART and DuCNoC, but unlike HEROv2, the remainder of the computer system remains in a higher-level simulator that injects traffic into the on-chip network.…”

Section: Related Workmentioning

confidence: 99%

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

Kurth¹,

Forsberg²,

Benini³

2022

Preprint

View full text Add to dashboard Cite

Heterogeneous computers integrate general-purpose host processors with domain-specific accelerators to combine versatility with efficiency and high performance. To realize the full potential of heterogeneous computers, however, many hardware and software design challenges have to be overcome. While architectural and system simulators can be used to analyze heterogeneous computers, they are faced with unavoidable compromises between simulation speed and performance modeling accuracy. In this work we present HEROv2, an FPGA-based research platform that enables accurate and fast exploration of heterogeneous computers consisting of accelerators based on clusters of 32-bit RISC-V cores and an application-class 64-bit ARMv8 or RV64 host processor. HEROv2 allows to seamlessly share data between 64-bit hosts and 32-bit accelerators and comes with a fully open-source on-chip network, a unified heterogeneous programming interface, and a mixed-data-model, mixed-ISA heterogeneous compiler based on LLVM. We evaluate HEROv2 in four case studies from the application level over toolchain and system architecture down to accelerator microarchitecture. We demonstrate how HEROv2 enables effective research and development on the full stack of heterogeneous computing. For instance, the compiler can tile loops and infer data transfers to and from the accelerators, which leads to a speedup of up to 4.4× compared to the original program and in most cases is only 15 % slower than a handwritten implementation, which requires 2.6× more code.

show abstract

“…By running specific scenarios, these tools help to determine channel and buffer sizing, project routing and switching techniques, assess communication performance, specify packet format, and avoid starvation caused by deadlocks. NoC simulation tools have been adopted academically and by the industry in the last years [3,4,5,6,7,8,9,10,11,12,13,14,15]. However, most of these tools present a complex interface and require extra runtime and knowledge when explored together with hardware simulation tools.…”

Section: Introductionmentioning

confidence: 99%

A Multi-Agent-Based Network-on-Chip Simulator

Lima

Adamatti

Brião

et al. 2021

JICS

View full text Add to dashboard Cite

Integrated systems have incorporated a variety of functionalities within the same chip, requiring on-chip communication mainly based on the Network-on-Chip (NoC) design paradigm. Complex systems may impose strict requirements concerning performance, power and reliability. Thus, the choice of proper routing algorithms to the on-chip communication for NoCs merits special attention. To assist designers to adjust communication parameters, implement routing algorithms, and check system correctness, simulators become powerful and cost-effective solutions. This article explores Multi-Agent System to develop a high level abstraction NoC simulation environment. The simulator allows designers to evaluate routing algorithms, test alternative configurations and message formats. The simulation provides important measurementssuch as rate of utilization of routers, network contention and delay in sending messages. As a case study, the XY and WF routing algorithms were modeled and analyzed. Results highlight the pros and cons of each algorithm, and outline the simulator overall performance.

show abstract

DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture

Cited by 22 publications

References 24 publications

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

A Multi-Agent-Based Network-on-Chip Simulator

Contact Info

Product

Resources

About