Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Balamurugan, K.; Umamaheswaran, S.; Mamo, Tadele; Nagarajan, Srikantan S.; Namamula, Lakshmana Rao

doi:10.1088/2399-6528/ac4dd5

Cited by 6 publications

(3 citation statements)

References 45 publications

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“…4 ML techniques are employed in both existing and new NoCs. 5 QoS is critical for validating NoC performance in various traffic scenarios. The congestion in NoC can be caused by inefficient traffic mapping, non-optimal flow control, non-uniform traffic routing, and improper network topologies.…”

Section: Introductionmentioning

confidence: 99%

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A deep learning based latency aware predictive routing model for network‐on‐chip architectures

Sudhakar,

Reddy,

Penchalaiah

et al. 2023

Int J Communication

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SummaryNetwork on Chip (NoC) is an evolving platform for communications related applications, which are executed on a single silicon chip. There are several routing models in NoC architectures, but the accuracy of these models is limited, and the existing models are degraded because of over and under fitting issues. This research introduces the new deep learning‐based latency aware predictive routing model for on‐chip networks to route packets with better performance and power efficiency. The deep learning model used in this research is a new convolutional residual gated recurrent unit (CRGRU) with queuing theory. Moreover, the source and channel queuing delay is comprised of features to learn spatial and sequential information that improves the overall prediction accuracy. This router is modified by the intrusion of the Router States Monitor unit and the CRGRU hardware engine. The work is executed using the Xilinx platform, and the performance measures like latency and throughput are obtained by varying the network size as , , and and also varying the buffer space and length as , , and , respectively. In addition, the squared correlation coefficient (SCC) and normalized root mean square error (NRMSE) are evaluated and compared with existing learning models to validate the proposed model.

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Section: Introductionmentioning

confidence: 99%

“…ML techniques are employed in both existing and new NoCs 5 . QoS is critical for validating NoC performance in various traffic scenarios.…”

Section: Introductionmentioning

confidence: 99%

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

Sudhakar,

Reddy,

Penchalaiah

et al. 2023

Int J Communication

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“…Chip peeling and transfer are widely used for the packaging and manufacturing of high-performance devices, such as CPU, DSP, LED, RFID, and MEMERY, and represent the key to enhancing the performance and reliability of electronic devices. At present, chips are constantly developing in the direction of thinness, high performance, and low power consumption [5][6][7]. The industry IC chip thickness has been reduced from 120 µm to less than 40 µm, and those used in laboratory applications have reached the level of 10~20 µm.…”

Section: Introductionmentioning

confidence: 99%

Coupled Excitation Strategy for Crack Initiation at the Adhesive Interface of Large-Sized Ultra-Thin Chips

Chen

Wen

et al. 2023

Processes

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The initial excitation of interface crack of large-size ultra-thin chips is one of the most complicated technical challenges. To address this issue, the reversible fracture characteristics of a silicon-based chip (chip size: 1.025 mm × 0.4 mm × 0.15 mm) adhesive layer interface was examined by scanning electron microscope (SEM) tests, and the characteristics of a cohesive zone model (CZM) unit were obtained through peel testing. The fitting curve of the elastic bilinear model was in high agreement with the experimental data, with a correlation coefficient of 0.98. The maximum energy release rate required for stripping was GC = 10.3567 N/m. Subsequently, a cohesive mechanical model of large-size ultra-thin chip peeling was established, and the mechanical characteristics of crack initial excitation were analyzed. The findings revealed that the larger deflection peeling angle in the peeling process resulted in a smaller peeling force and energy release rate (ERR), which made the initial crack formation difficult. To mitigate this, a coupling control method of structure and force surface was proposed. In this method, through structural coupling, the change in chip deflection was greatly reduced through the surface coupling force, and the peeling angle was greatly improved. It changed the local stiffness of the laminated structure, made the action point of fracture force migrate from the center of the chip to near the edge of the chip, the peeling angle was increased, and the energy release rate was locally improved. Finally, combined with mechanical analysis and numerical simulation of the peeling process, the mechanical characteristics of peeling were analyzed in detail. The results indicated that during the initial crack germination process, the ERR of the peel interface is significantly increased, the maximum stress value borne by the chip is significantly reduced, and the peel safety and reliability are greatly improved.

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A hybrid crossbar-ring on chip network topology for performance improvement of multicore architectures

Joshi,

Ramasubramanian

2023

Int. j. inf. tecnol.

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Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Cited by 6 publications

References 45 publications

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

A deep learning based latency aware predictive routing model for network‐on‐chip architectures

Coupled Excitation Strategy for Crack Initiation at the Adhesive Interface of Large-Sized Ultra-Thin Chips

A hybrid crossbar-ring on chip network topology for performance improvement of multicore architectures

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