Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.
DOI: 10.1109/.2005.1469192
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Dual stress liner enhancement in hybrid orientation technology

Abstract: Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown (110) bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I DSat at 100 nA/um I OFF for V DD =1.0 V at a 45 nm gate l… Show more

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Cited by 18 publications
(5 citation statements)
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“…A direct way to introduce stress in a MOSFET's channel is to fill the source and drain regions with SiGe [23,24] for p-channel MOSFETs and with SiC for n-channel MOSFTEs [25,26]. Additional uniaxial stress is often introduced by growing compressive or tensile capping layers [27][28][29]. The advantage of local stress techniques is that they can be combined [30] and superimposed [31] on the same wafer.…”
Section: Strain Engineering Techniquesmentioning
confidence: 99%
“…A direct way to introduce stress in a MOSFET's channel is to fill the source and drain regions with SiGe [23,24] for p-channel MOSFETs and with SiC for n-channel MOSFTEs [25,26]. Additional uniaxial stress is often introduced by growing compressive or tensile capping layers [27][28][29]. The advantage of local stress techniques is that they can be combined [30] and superimposed [31] on the same wafer.…”
Section: Strain Engineering Techniquesmentioning
confidence: 99%
“…Fabricating PMOS transistors on a (110) and NMOS transistors on a (100) surface orientations will enhance CMOS performance significantly. Monolithic integration of (110) PMOS and (100) NMOS has been demonstrated with the use of Hybrid Orientation Technology (HOT) [12,13]. Short channel devices and circuits that were fabricated using (110) surface demonstrated a gain of about 20% in the drive current for PMOS with gate length of 50 nm.…”
Section: Dual Channel Engineeringmentioning
confidence: 99%
“…Recently, channel engineering techniques, such as introducing strain, 1) incorporating Ge, 2) and using different substrate orientations, 3,4) to improve the performance of field effect transistors (FETs) have attracted a great deal of interest. In the case of substrate orientation, it has been shown that the electron mobility of n-type metal-oxidesemiconductor (n-MOSFETs) is highest in Si(100), whereas the hole mobility of p-MOSFETs is maximum in Si(110).…”
Section: Introductionmentioning
confidence: 99%