2013
DOI: 10.1049/el.2012.4126
|View full text |Cite
|
Sign up to set email alerts
|

Dual‐metastability FPGA‐based true random number generator

Abstract: A novel concept of a true random number generator (TNRG) based on two metastable flip-flops in a FPGA circuit is introduced. Most of metastable based TRNG solutions are based on the assumption of a D-latch (flip-flop) state's uncertainty which is the source of randomness. In the proposed approach direct proximity of the metastable point is not necessary. Difference of the time of response of a pair of nearly metastable flip-flops lies upon the proposed circuit's principle of operation. It can be implemented in… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
9
0
1

Year Published

2015
2015
2020
2020

Publication Types

Select...
5
2
1

Relationship

0
8

Authors

Journals

citations
Cited by 18 publications
(10 citation statements)
references
References 8 publications
0
9
0
1
Order By: Relevance
“…As it was expected, using low clock frequencies (4,8,20, and 32 MHz), the power glitches do not impact the final output due to the fact that the critical path delay period is still lower than the clock frequency. However, using a 40 MHz clock and a power glitch length of 10 000 clock cycles, i.e., 250 μs, a bias appears at the TRNG output before the post-processing is done.…”
Section: ) Nominal Supply Voltagementioning
confidence: 51%
See 2 more Smart Citations
“…As it was expected, using low clock frequencies (4,8,20, and 32 MHz), the power glitches do not impact the final output due to the fact that the critical path delay period is still lower than the clock frequency. However, using a 40 MHz clock and a power glitch length of 10 000 clock cycles, i.e., 250 μs, a bias appears at the TRNG output before the post-processing is done.…”
Section: ) Nominal Supply Voltagementioning
confidence: 51%
“…For different frequencies (4,8,10, and 20 MHz) and a core voltage of 1.20 V, clock glitches were injected without observable effect in the output. This is due to the fact that the highest frequency For a STR configuration of 255 stages, setting the core voltage to 1.20 V, and using a clock frequency of 40 MHz, clock glitches were injected generating a faulty output in the TRNG.…”
Section: Clock-glitch Attacksmentioning
confidence: 99%
See 1 more Smart Citation
“…Wieczorek presented a dual-metastability time-competitive generator. Empirical and statistical test results of random number that take from the generator are successful [26].…”
Section: R4mentioning
confidence: 99%
“…Ornegin, kosmik giiriiltu, elektronik gurUllli, X-I�llllasl gibi bir vok kaynaktan elde edilen saYIsal i�aretler insan mudahalesinden uzak olmasl ve veri Uretirn slirecinin ongorUlemez olmasl sebebiyle, yUksek rasgelelik ozelligine sahip oldugu kabul edilmektedir. Farkh bir vok dagmtkltk kaynagl ba�an ile kullallllmaktadrr [4][5][6][7]. Dagmlkltk kaynagmm gozlemlerinden elde edilmi� saYlsal orneklerin ozellikle son bitinin yfi ksek rasgelelik ozelligine sahip oldugu, oysa ilk ornekleme saYlsmm ise, dii�uk frekansa sahip olabileeeginden dolaYl, dii�uk rasgelelige sahip oldugu bilinmektedir.…”
Section: Sa Yisal Radyo Frekans Isareti Orneklerinin Elde Edilmesiunclassified