Dual-Interlocked Logic for Single-Event Transient Mitigation

Maharrey, J. A.; Kauppila, J. S.; Harrington, R. C.; Nsengiyumva, Patrick; Ball, D. R.; Haeffner, T. D.; Zhang, E. X.; Bhuva, B. L.; Holman, W.T.; Massengill, L.W.

doi:10.1109/tns.2017.2783239

“…The results show a considerable increase in the charge needed to upset the node [8]. In another work, the dual-interlocked logic family demonstrates to be more robust to single event transient (SET) propagation even for dual-node strikes with a beneficial tradeoff in area and power [9].…”

Section: Circuit Design For Improve the Reliabilitymentioning

confidence: 97%

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

Zimpeck

¹

,

Meinhardt

²

,

Artola

³

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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This paper evaluates the potential of using the sleep transistor in FinFET logic cells to mitigate the process variability effects and the soft error susceptibility. The insertion of a sleep transistor improves up to 40.6% the delay variability and up to 12.4% the power variability. Moreover, the design with a sleep transistor became all logic cells investigated free of faults, independently of the supply voltage applied in the design.

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“…The foundry worst case libraries are a good stand-in for modelling radiation damage. All weights are stored in registers and no SRAMs or DICE cells [27] are used. Fig.…”

Section: Integrated Converter Encoder and Imentioning

confidence: 99%

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

Guglielmo

¹

,

Fahim

²

,

Herwig

³

et al. 2021

IEEE Trans. Nucl. Sci.

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Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network autoencoder model can be implemented in a radiation tolerant ASIC to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the CMS experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the neural network weights, a unique data compression algorithm can be deployed for each sensor in different detector regions, and changing detector or collider conditions. To meet area, performance, and power constraints, we perform a quantizationaware training to create an optimized neural network hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework, and was processed through synthesis and physical layout flows based on a LP CMOS 65 nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates, and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. This is the first radiation tolerant on-detector ASIC implementation of a neural network that has been designed for particle physics applications.

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“…The foundry worst case libraries are a good stand-in for modelling radiation damage. All weights are stored in registers and no SRAMs or DICE cells [27] are used. Single Event Effect Mitigation: Mitigating single-event effects (SEEs) is a critical step in the ASIC implementation for effective performance in the HL-LHC environment.…”

Section: Architectural Explorationmentioning

confidence: 99%

A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC

Di Guglielmo,

Fahim,

Herwig

et al. 2021

Preprint

1

0

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Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network autoencoder model can be implemented in a radiation tolerant ASIC to perform lossy data compression alleviating the data transmission problem while preserving critical information of the detector energy profile. For our application, we consider the high-granularity calorimeter from the CMS experiment at the CERN Large Hadron Collider. The advantage of the machine learning approach is in the flexibility and configurability of the algorithm. By changing the neural network weights, a unique data compression algorithm can be deployed for each sensor in different detector regions, and changing detector or collider conditions. To meet area, performance, and power constraints, we perform a quantizationaware training to create an optimized neural network hardware implementation. The design is achieved through the use of high-level synthesis tools and the hls4ml framework, and was processed through synthesis and physical layout flows based on a LP CMOS 65 nm technology node. The flow anticipates 200 Mrad of ionizing radiation to select gates, and reports a total area of 3.6 mm 2 and consumes 95 mW of power. The simulated energy consumption per inference is 2.4 nJ. This is the first radiation tolerant on-detector ASIC implementation of a neural network that has been designed for particle physics applications.

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Dual-Interlocked Logic for Single-Event Transient Mitigation

Cited by 14 publications

References 15 publications

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

A Reconfigurable Neural Network ASIC for Detector Front-End Data Compression at the HL-LHC

A reconfigurable neural network ASIC for detector front-end data compression at the HL-LHC

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