Dual Die Pentium D Package Technology Development

Manusharow, M.; Hasan, A.; Chao, Tong Wa; Guzy, M.T.

doi:10.1109/ectc.2006.1645663

Cited by 9 publications

(3 citation statements)

References 2 publications

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“…To improve the cooling efficiency, packages such as D2PAK, D-PAK, Power SOP and MLP are broadly used [7]. The heat flow path is inefficient in these packages because the generated thermal energy has to travel through the chip, solder, copper frame, footprint, epoxy and finally dissipates into the PCB and ambient.…”

Section: Problem Identification and Technical Analysismentioning

confidence: 99%

Advanced VRM Incorporated with 3D DCB Package for Computor Power Management Applications

Jin

2012

2012 IEEE 14th International Conference on High Performance Computing and Communication &Amp; 2012 IEEE 9th International Confe

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This paper proposed a voltage regulator module (VRM) integrated with 3D Direct Copper Bonded (DCB) packaging technology for advanced computation applications. Technical analysis has been undertaken to investigate the multifaceted features of existing technologies in a computer system. Addressing on the technology challenges, i.e. parasitic effect and overheating issues, a 3D DCB packaged VRM is developed in this work. Its configuration is designated to improve the effectiveness in mitigating both issues, and the results are subsequently evaluated by multiphysics simulation. The results show the internal parasitic inductance of VRM has been reduced to 0.19nH in contrast to the 10nH of conventional approaches, and the 3D package leads to improved cooling efficiency for computer power management applications.

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Section: Problem Identification and Technical Analysismentioning

confidence: 99%

Advanced VRM Incorporated with 3D DCB Package for Computor Power Management Applications

Jin

2012

2012 IEEE 14th International Conference on High Performance Computing and Communication &Amp; 2012 IEEE 9th International Confe

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“…Thermal control is one most critical issue for both operating performance and long-term reliability thereof. To improve the packaging thermal efficiency, packages such as D2PAK, D-PAK, Power SOP and MLP are broadly accepted approaches [5][6][7][8]. In these packages, heat generated at the face of the die has to travel through the bulk of the silicon and through the heat sink to be finally dissipated through the printed circuit board and the ambient.…”

Section: Technology Analysismentioning

confidence: 99%

A cool packaging technology for power conversion application

Jin

2011

2011 IEEE International Conference on Computer Science and Automation Engineering

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Power management relieves critical bottlenecks in saving electrical energy and efficient switching devices are particularly required for synchronous power conversion module. To optimize both switching and thermal efficiencies for convertor configuration it relies on the advanced package technology. An analysis has been undertaken in this work to identify the challenge on power electronic packages to ensure the system efficiencies continue to increase. This paper presents an innovative three-dimension (3D) packaging technology -CoolPAK, which enables high voltage, high frequency and high reliable voltage switching with reduced power loss in thermal dissipation.

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“…For high volume manufacturing (HVM), evolution went through different steps. It was initially going from a single die package to a multi-chip-module packaging in 2006, 1 now known as two-dimensional packaging, where two or more dies were connected on the same package substrate with communication channels through high-frequency serializer/deserializer (SerDes) that were designed into the organic package substrate. Then, system-on-chip (SoC) appeared by integrating the different components of a comprehensive system on a single silicon substrate.…”

Section: Introductionmentioning

confidence: 99%

Minimizing die fracture in 3DIC die integration

Bravo,

Morey-Chaisemartin,

Beisser

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: The demand for high-performance semiconductor products has led to reduced wafer feature size, lowered package size, and an ever-thinner die for advanced three-dimensional (3D) packaging. Dies down to a thickness of 5 μm have been demonstrated. One significant barrier is the fragility of the thin dies, their overall thin form factor, and their impact on yield, reliability, and costs.Aim: We explore the current state of the art in the current crack stop and outline the shortcomings moving forward for stacked 3D integrated circuits (3DIC).Approach: Using a theoretical understanding of fracture mechanics and the new biomimetic concept adapted from nature, we show the implementation of the new crack stop insertions in the die frame for a next-generation 3DIC product. Results:The proposed crack stop can be easily inserted in the die frame with electronic design automation (EDA) tools using a Python interpreter and has the capability to arrest a crack near its initiation point. Conclusions:We show the feasibility of the implementation through EDA tools and outline the next step.

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Dual Die Pentium D Package Technology Development

Cited by 9 publications

References 2 publications

Advanced VRM Incorporated with 3D DCB Package for Computor Power Management Applications

Advanced VRM Incorporated with 3D DCB Package for Computor Power Management Applications

A cool packaging technology for power conversion application

Minimizing die fracture in 3DIC die integration

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