Driver modeling and alignment for worst-case delay noise

Sirichotiyakul, Supamas; Blaauw, David; Oh, Chang-Hwan; Levy, R.; Zolotov, Vladimir; Zuo, Jingyan

doi:10.1145/378239.379054

Cited by 51 publications

(56 citation statements)

References 9 publications

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“…Crosstalk noise not only leads to modified delays [2], [ 3] but also to potential logic malfunctions [4], [ 5]. To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Hunagund¹,

Kalpana²

2011

IJET

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Abstract-Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 3GHz has caused crosstalk noise to become a serious problem that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width to estimate on-chip crosstalk noise and also shown that crosstalk can be minimized by wire spacing and wire sizing optimization technique. These models are verified for various deep submicron technologies.Index Terms-Aggressor, Coupling, Crosstalk, Interconnect noise, Wire spacing, I. INTRODUCTIONAdvancement in the field of very large scale integration (VLSI) have lead to a decrease in device geometries (deep submicron technology), high device densities, high clock rates, and thus small signal transition times. Thus, interconnection lines that were once considered to be electrically isolated can now interfere with each other and have an important impact on system performance and correctness. One such interaction caused by parasitic coupling between wires is known as crosstalk. If not carefully considered during design validation, crosstalk can cause extra signal delay, logic hazards, and even circuit malfunction. Accurate modeling and simulation of interconnect delay due to crosstalk thus becomes increasingly important in the design of high-performance integrated circuits.The net on which noise is being induced is called the victim net whereas the net that induces this noise is called the aggressor net. Crosstalk noise not only leads to modified delays [2], [ 3] but also to potential logic malfunctions [4], [ 5]. To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages. Any such tool requires fast yet accurate crosstalk noise models both to estimate noise and also to see the effects of Manuscript received September 19, 2011; revised December 3, 2011. P. V. Hunagund is with the Department of Applied Electronics, Gulbarga University, Gulbarga, India (e-mail:prabhakar.hunagund@gmail.com).A. B. Kalpana is with the Electronics and Communication Engineering Department, Bangalore Institute of Technology, Bangalore, India (e-mail: abkalpana@gmail.com).various interconnect and driver parameters on noise. Several papers, which propose crosstalk models, can be found in recent literature. In [6], telegraph equations are solved directly to find a set of analytical formulae for peak noise in capacitively coupled bus lines. [7] derives bounds for crosstalk noise using a lumpe...

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Section: Introductionmentioning

confidence: 99%

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Hunagund¹,

Kalpana²

2011

IJET

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“…For this purpose, conventional methods [1][2][3][4][5][6] estimate the Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.…”

Section: Introductionmentioning

confidence: 99%

“…[2]. References [3][4][5] discuss how to estimate the worst-case delay. The methods [1,3,4,6] evaluate the delay variation at the end of the coupled interconnects.…”

Section: Introductionmentioning

confidence: 99%

“…The methods [1,3,4,6] evaluate the delay variation at the end of the coupled interconnects. However the 50% crossing time of crosstalk-induced noisy waveform at the end of the coupled interconnect is meaningless, because the noisy waveform itself affects the propagation delay of the next receiver gate [5]. We therefore have to evaluate crosstalk noise effects including the receiver gate.…”

Section: Introductionmentioning

confidence: 99%

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Capturing crosstalk-induced waveform for accurate static timing analysis

Hashimoto

Yamada

Onodera

2003

Proceedings of the 2003 International Symposium on Physical Design

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We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally measured as delay variation. On the other hand, the propose method derives an equivalent waveform to a crosstalk-induced noisy waveform. The crosstalk effects on timing are all included in the equivalent waveform. With the derived equivalent waveform, we can perform static timing analysis with consideration of dynamic delay variation due to crosstalk noise. The equivalent waveform is derived by our improved least square fitting with weighting coefficient. Our method can naturally consider the slew variation due to crosstalk noise as well as the delay variation. We experimentally verify that our method can estimate the delay variation at the output of the receiver gate accurately. The strength is that the proposed method requires no additional library characterization and is easy to be integrated into usual static timing analysis methods.

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“…Recently, the problem of crosstalk noise discussed in Section II-A is raised in [8], which estimates the output waveforms against noisy input waveforms using look-up tables. This look-up table has two additional parameters of noise width and noise height as well as usual load and input slope.…”

Section: B Previous Workmentioning

confidence: 99%

Equivalent waveform propagation for static timing analysis

Hashimoto¹,

Yamada²,

Onodera³

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Abstract-This paper proposes a scheme that captures diverse input waveforms of CMOS gates for static timing analysis (STA). Conventionally latest arrival and transition times are calculated from the timings when a transient waveform goes across predetermined reference voltages. However, this method cannot accurately consider the impact of waveform shape on gate delay when crosstalk-induced nonmonotonic waveforms or inductance-dominant stepwise waveforms are injected. We propose a new timing analysis scheme called "equivalent waveform propagation." The proposed scheme calculates the equivalent waveform that makes the output waveform close to the actual waveform, and uses the equivalent waveform for timing calculation. The proposed scheme can cope with various waveforms affected by resistive shielding, crosstalk noise, wire inductance, etc. In this paper, we devise a method to calculate the equivalent waveform. The proposed calculation method is compatible with conventional methods in gate delay library and characterization and, hence, our method is easily implemented with conventional STA tools.

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Driver modeling and alignment for worst-case delay noise

Cited by 51 publications

References 9 publications

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Capturing crosstalk-induced waveform for accurate static timing analysis

Equivalent waveform propagation for static timing analysis

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