DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Lin, Yibo; Jiang, Zixuan; Gu, Jiaqi; Li, Wuxi; Dhar, Shounak; Ren, Haoxing; Khailany, Brucek; Pan, David Z.

doi:10.1109/tcad.2020.3003843

Cited by 88 publications

(78 citation statements)

References 32 publications

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“…We implemented our parallel RePlAce in C++ and built it with g++ version 7.3.0 and -O3 optimization. We benchmark placement without dynamic step size adaptation or local density, to enable a direct comparison to DREAMPlace [5]. The initial placement uses the Eigen library with multithreading enabled; detailed placement is performed using the NTU-Place3 binary.…”

Section: Resultsmentioning

confidence: 99%

“…Table II reports results for our sequential implementation of RePlACe using our proposed efficient data structures and our multithreaded parallel implementation with 1, 2, 4, 8, and 12 threads. We compare directly to RePlAce, a multithreaded version of RePlAce (12 threads) [3], and DREAMPlace (12 threads, no GPU) [5]. As an example, we reduced the time to place BIGBLUE4 benchmark by a factor of 2.36×, which amounts to 33 minutes saved.…”

Section: Resultsmentioning

confidence: 99%

“…Their GPU-accelerated bin density yields speedups from 4.3× to 7×. The most recent GPU-placer is DREAMPlace [5]. It is built on the idea of using features from machine learning frameworks (PyTorch specifically), such as the nonlinear optimization engine.…”

Section: Related Workmentioning

confidence: 99%

“…RePlAce extends ePlace with a fast nonlinear engine for standard-cell, mixed-size, and 3D-IC mixed-size placement, achieving superior results and a lower runtime than ePlace; however, RePlAce still requires hours to legally place industrial-grade circuits. Recent placer DREAMPlace considerably reduces the runtime using PyTorch's engine, but, for the moment, it runs efficiently only on GPUs [5].…”

Section: Introductionmentioning

confidence: 99%

“…• At 12 CPU threads, ≈3× speedup over RePlAce [3] and ≈3.5× speedup over DREAMPlace [5] running on CPU. The rest of the paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

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A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Gessler

Brisk

Stojilović

2020

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)

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RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell placement, while achieving shorter wirelength and similar or shorter runtimes than other state-of-the-art placers on the ISPD-2005/2006 standard-cell benchmarks; however, the runtime of RePlAce on these benchmarks ranges from 15 minutes to 5+ hours on a 2.6 GHz Intel Xeon server running a single thread, rendering development cycles prohibitively long. To address this concern, this paper introduces a multi-threaded shared-memory implementation of RePlAce. The contributions include techniques to reduce memory contention and to effectively balance the workload among threads, targeting the most substantial performance bottlenecks. With 2-12 threads, our parallel RePlAce speeds up the bin density function by a factor of 4.2-10×, the wirelength function by a factor of 2.3-3×, and the cost gradient function by a factor of 2.9-6.6× compared to the single-threaded original RePlAce baseline. Moreover, our parallel RePlAce is ≈3.5× faster than the state-of-the-art PyTorch-based placer DREAMPlace, when both are running on 12 CPU cores.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…• At 12 CPU threads, ≈3× speedup over RePlAce [3] and ≈3.5× speedup over DREAMPlace [5] running on CPU. The rest of the paper is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Gessler

Brisk

Stojilović

2020

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)

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14‐4: Efficient Multi‐stage Bayesian Optimization for Optimal Display Circuit Input Signal Design

Bliesener,

Wang,

et al. 2023

Symp Digest of Tech Papers

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To correct for threshold variations in the driving transistor, pixel circuits rely on a complex sequence of inputs that drive the circuit through programming and emission phase. In this work we propose a multi‐stage optimization strategy to automate the design of input signals for arbitrary pixel circuits. By solving for the operation phases of pixel circuits separately and in reverse order our algorithm efficiently finds the narrow region of input signal designs that achieve the desired functionality in the large search space. We demonstrate the generality of our algorithm on two common pixel circuits, i.e., 3T1C and 7T1C.

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The Solution of Huawei Cloud & Noah’s Ark Lab to the NLPCC-2020 Challenge: Light Pre-Training Chinese Language Model for NLP Task

Zhang

Wang

et al. 2020

Natural Language Processing and Chinese Computing

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The performance of Large Language Models (LLMs) in reasoning tasks depends heavily on prompt design, with Chain-of-Thought (CoT) and self-consistency being critical methods that enhance this ability. However, these methods do not fully exploit the answers generated by the LLM to guide subsequent responses. This paper proposes a new prompting method, named Progressive-Hint Prompting (PHP), that enables automatic multiple interactions between users and LLMs by using previously generated answers as hints to progressively guide toward the correct answers. PHP is orthogonal to CoT and self-consistency, making it easy to combine with state-of-the-art techniques to further improve performance. We conducted an extensive and comprehensive evaluation to demonstrate the effectiveness of the proposed method. Our experimental results on six benchmarks show that combining CoT and self-consistency with PHP significantly improves accuracy while remaining highly efficient. For instance, with text-davinci-003, we observed a 4.2% improvement on GSM8K with greedy decoding compared to Complex CoT, and a 46.17% reduction in sample paths with self-consistency. With GPT-4 and PHP, we achieve state-of-the-art performances on SVAMP (91.9%), GSM8K (95.5%) and AQuA (79.9%).Preprint. Under review.

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DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Cited by 88 publications

References 32 publications

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

14‐4: Efficient Multi‐stage Bayesian Optimization for Optimal Display Circuit Input Signal Design

The Solution of Huawei Cloud & Noah’s Ark Lab to the NLPCC-2020 Challenge: Light Pre-Training Chinese Language Model for NLP Task

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