DRAM Refresh Mechanisms, Penalties, and Trade-Offs

Bhati, Ishwar; Chang, Mu-Tien; Chishti, Zeshan; Lu, Shih-Lien; Jacob, Bruce

doi:10.1109/tc.2015.2417540

Cited by 108 publications

(50 citation statements)

References 22 publications

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“…This effective switching capacitance increases for higher-capacity DRAM devices. Hence, the refresh power consumption continues to increase as DRAM device capacity increases [1], [4], [18].…”

Section: B Refresh Operationsmentioning

confidence: 99%

On the Optimal Refresh Power Allocation for Energy-Efficient Memories

Kim

Choi

Guyot

et al. 2019

2019 IEEE Global Communications Conference (GLOBECOM)

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Refresh is an important operation to prevent loss of data in dynamic random-access memory (DRAM). However, frequent refresh operations incur considerable power consumption and degrade system performance. Refresh power cost is especially significant in high-capacity memory devices and battery-powered edge/mobile applications. In this paper, we propose a principled approach to optimizing the refresh power allocation. Given a model for the bit error rate dependence on power, we formulate a convex optimization problem to minimize the word mean squared error for a refresh power constraint; hence we can guarantee the optimality of the obtained refresh power allocations. In addition, we provide an integer programming problem to optimize the discrete refresh interval assignments. For an 8-bit accessed word, numerical results show that the optimized nonuniform refresh intervals reduce the refresh power by 29 % at a peak signal-tonoise ratio of 50 dB compared to the uniform assignment.

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Section: B Refresh Operationsmentioning

confidence: 99%

On the Optimal Refresh Power Allocation for Energy-Efficient Memories

Kim

Choi

Guyot

et al. 2019

2019 IEEE Global Communications Conference (GLOBECOM)

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“…DRAM needs to be refreshed periodically to prevent data loss. According to JEDEC [22], 8K all-bank auto-refresh (REF) commands are sent to all DRAM devices in a rank within one retention time interval (Tret), also called as one refresh window (tREFW) [7,40,10], typically 64ms for DDRx. The gap between two REF commands is termed as refresh interval (tREFI), whose typical value is 7.8μs, i.e.…”

Section: Dram Basicsmentioning

confidence: 99%

“…While upgrading refresh rate reduces restore time, it generates more real refresh commands, which not only prolongs memory unavailable period but also consumes more refresh energy. Previous work shows that refresh may consume over 20% of the total memory energy for a 32Gb DRAM device [7,36]. Blindly upgrading the refresh rate of all rows is thus not desirable.…”

Section: Rt-select: Proactive Refresh Rate Upgradementioning

confidence: 99%

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Restore truncation for performance improvement in future DRAM systems

Zhang

Childers

et al. 2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Scaling DRAM below 20nm has become a major challenge due to intrinsic limitations in the structure of a bit cell. Future DRAM chips are likely to suffer from significant variations and degraded timings, such as taking much more time to restore cell data after read and write access.In this paper, we propose restore truncation (RT), a lowcost restore strategy to improve performance of DRAM modules that adopt relaxed restore timing. After an access, RT restores a bit cell's voltage only to the level required to persist data to the next scheduled refresh rather than to the default full voltage. Because restore time is shortened, the performance of the cell is improved under process variations. We devise two schemes to balance performance, energy consumption, and hardware overhead. We simulate our proposed RT schemes and compare them with the state of the art. Experimental results show that, on average, RT improves performance by 19.5% and reduces energy consumption by 17%.

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“…Though the main problem of high temperature in ICs is a reliability issue [4], DRAM cells have one more important problem under high temperature: refresh rates. The typical DRAM refresh interval is 64 ms [5] while it is reduced to 32 ms (by half ) when temperature is over 85°C to ensure data integrity. Since reduced refresh interval adversely affects both performance and energy-efficiency, it is crucial to manage DRAM temperature so that it does not go beyond 85°C.…”

Section: Introductionmentioning

confidence: 99%

3D die-stacked DRAM thermal management via task allocation and core pipeline control

Yoon

Shim

Moon

et al. 2018

IEICE Electron. Express

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A major hurdle to adopt 3D stacked DRAM is a thermal problem particularly when the DRAM dies are stacked above the processor dies. Exacerbated thermal problems in DRAM cause another problem which increases refresh rates to ensure data integrity of DRAM cells. In this paper, we propose two efficient techniques to address the thermal problem in 3D die-stacked DRAM by suppressing adverse thermal impacts from the processor die. Our thermal-aware task mapping technique allocates tasks to cores by considering computation-intensiveness of the workloads to minimize thermal interactions. The workload-aware core pipeline control technique adjusts pipeline widths (fetch and issue widths) of processor cores considering the workload characteristics. By adopting our proposed techniques, system-wide energy consumption is reduced by 7.6% while improving performance by 0.4% on average, thanks to the reduced pipeline widths and refresh rates. In terms of temperature, our techniques reduce the number of DRAM banks which exceed 85 degree Celsius by 92.8%, on average.

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DRAM Refresh Mechanisms, Penalties, and Trade-Offs

Cited by 108 publications

References 22 publications

On the Optimal Refresh Power Allocation for Energy-Efficient Memories

On the Optimal Refresh Power Allocation for Energy-Efficient Memories

Restore truncation for performance improvement in future DRAM systems

3D die-stacked DRAM thermal management via task allocation and core pipeline control

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