Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

Raad, Bhagwan Ram; Sharma, Dheeraj; Kondekar, P. N.; Nigam, Kaushal; Yadav, Dharmendra Singh

doi:10.1109/ted.2016.2600621

Cited by 102 publications

(34 citation statements)

References 36 publications

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“…Figure 5b shows the energy band profile at the ON-state. An energy peak is created near the drain/channel interface, which will act as a barrier for electrons tunneling from the source to the drain region at the positive bias [28]. Therefore, I ON of DE-HTFET with φ M = 5.3 eV significantly degrades as shown in Figure 4.…”

Section: Resultsmentioning

confidence: 99%

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Duan¹,

Zhang²,

Chen³

et al. 2019

Micromachines

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A drain engineered InGaN heterostructure tunnel field effect transistor (TFET) is proposed and investigated by Silvaco Atlas simulation. This structure uses an additional metal on the drain region to modulate the energy band near the drain/channel interface in the drain regions, and increase the tunneling barrier for the flow of holes from the conduction band of the drain to the valence band of the channel region under negative gate bias for n-TFET, which induces the ambipolar current being reduced from 1.93 × 10−8 to 1.46 × 10−11 A/μm. In addition, polar InGaN heterostructure TFET having a polarization effect can adjust the energy band structure and achieve steep interband tunneling. The average subthreshold swing of the polar drain engineered heterostructure TFET (DE-HTFET) is reduced by 53.3% compared to that of the nonpolar DE-HTFET. Furthermore, ION increases 100% from 137 mA/mm of nonpolar DE-HTFET to 274 mA/mm of polar DE-HTFET.

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Section: Resultsmentioning

confidence: 99%

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Duan¹,

Zhang²,

Chen³

et al. 2019

Micromachines

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“…To solve these problems, recently several new concepts have been explored (i.e.) work function engineering at gate and drain region [21,22], employment of metal strip at S/C region [23], high-K dielectric [5], and gate overlapping over the drain region [24]. Furthermore, using of dual work function at control gate (CG) region will resolve the issue of ambipolarity up to some extends and analogue/RF performances also limited [22].…”

Section: Introductionmentioning

confidence: 99%

“…Dual metal drain reduces the device characteristics performance of device [21] and other high-K materials and gate drain overlapping somewhat escalations the parasitic capacitance in comparison with conventional device [25]. Additionally, by using these ideas [21][22][23], the fabrication complexity arises at nano-scale.…”

Section: Introductionmentioning

confidence: 99%

Approach on electrically doped TFET for suppression of ambipolar and improving RF performance

Chandan

Nigam

Sharma

2019

IET Circuits, Devices & Systems

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In this editorial, the effect of dual gate underlap has been implemented on ED-TFET and it is named as underlap dual metal gate electrically doped tunnel FET (UL-DMG-ED-TFET). The proposed device has been reviewed in terms of device characteristics and analogue/radio-frequency figure of metrics. By using underlap theory, the authors have resolved the issues of ambipolarity and gate leakage current but somewhat C gd also increases without affecting the DC performances. Moreover, the authors have implemented the dual gate on the proposed device which helps to improve the DC and RF FOMs. Furthermore, the inversion layer and C gd inversion along with parasitic capacitances also deliberate on proposed device (UL-DMG-ED-TFET). Finally, the dual gate-underlap provides better DC and analogue/RF performances in comparison over conventional structure.

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“…Hetero-gate oxide CPTFET (HGO-CPTFET) induces large amount of charge carriers at the source and channel regions causing an increase in the rate of BTBT. Due to this, there is an intense improvement in the ON-state current of the device [8].…”

Section: Introductionmentioning

confidence: 99%

Hetero‐material CPTFET with high‐frequency and linearity analysis for ultra‐low power applications

Yadav

Sharma

Tirkey

et al. 2018

Micro & Nano Letters

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In this work, the authors have focused on increasing the current driving capability, speed of operation, suppression of parasitic capacitance and ambipolarity of the charge plasma tunnel field effect transistor (CPTFET). Gate dielectric and hetero-material engineering are employed in the CPTFET to obtain better drain current. Introduction of high-k dielectric increases the injection of charge carriers in the intrinsic body while a low-energy bandgap III-V material reduces the tunnelling width leading to the increased rate of band-to-band tunnelling of electrons and thus, enhancing the ON-state current of the device. Hence, the proposed device shows superior performance when operated in regime of DC and high frequency. For reducing the ambipolar conduction in the device, a widely used concept of underlapping of gate electrode is employed which reduces the leakage current in the device. Further, to determine the reliability of the device at high frequency, an analysis of linearity parameters is carried out. The proposed device is highly reliable to function at high-frequency regime. Therefore, the overall introduction of gate dielectric engineering, hetero-material engineering and underlapping of gate electrode improves the performance and characteristics of CPTFET.

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Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

Cited by 102 publications

References 36 publications

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

High Performance Drain Engineered InGaN Heterostructure Tunnel Field Effect Transistor

Approach on electrically doped TFET for suppression of ambipolar and improving RF performance

Hetero‐material CPTFET with high‐frequency and linearity analysis for ultra‐low power applications

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