DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs

Velegalati, Rajesh; Kaps, Jens-Peter

doi:10.1109/fpl.2009.5272260

Cited by 10 publications

(14 citation statements)

References 18 publications

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“…Separated DDL for FPGAs (SDDL for FPGAs) is a variant of DDL tailored for lightweight implementations on FPGAs [3]. It allows FPGA CAD tools to have maximum flexibility to optimize a given design for the target FPGA.…”

Section: Introductionmentioning

confidence: 99%

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic

Velegalati

Kaps

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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Block RAMs (BRAMs) are commonly used by implementations of cryptographic algorithms on Field Programmable Gate Arrays (FPGAs). Unfortunately, any hardware implementation of a cryptographic function is susceptible to differential power analysis (DPA) attacks unless it is protected. Dynamic and Differential Logic (DDL), a constant power consumption logic style, is the most popular and successful defense method against DPA attacks. The required Measurements to Disclosure (MTD) of the key has been shown to be larger than the life period of the secret key in most systems. DDL implementations on FPGAs proposed till date incur a large area overhead. In this paper we show that BRAMs can be used within a DDL design without compromising its security. We propose and analyze several implementation techniques for using BRAMs in DDL designs. Our results show that such DDL implementations increase the MTDs by a factor 4 over unprotected designs which use BRAMs and by a factor 2.5 over DDL implementations which do not use BRAMs.

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Section: Introductionmentioning

confidence: 99%

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic

Velegalati

Kaps

2010

2010 17th IEEE International Conference on Electronics, Circuits and Systems

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“…It is common design practice to separate the two parts of an SDDL design and place them side-by-side as in [5], [9]. Such placement strategy ensures that the two parts would have sufficient resources to obtain symmetrical delays.…”

Section: Placement Configurationmentioning

confidence: 99%

“…We duplicate and relocate the original design using the techniques described in [5]. Only re-entrant routing is done to connect the I/O to the Direct and Complementary parts of the design.…”

Section: A Placement Optionsmentioning

confidence: 99%

“…In the second phase logic precharge circuits implemented using the technique described in [9], [5] are inserted into the placed circuit description file obtained from phase 1. Only re-entrant routing is done to obtain a precharged placed and routed design.…”

Section: A Placement Optionsmentioning

confidence: 99%

“…SDDL for FPGAs, a variant of the SDDL style, was introduced in [5]. It is specifically designed as a countermeasure against DPA for lightweight or low area implementations on FPGAs.…”

Section: Introductionmentioning

confidence: 99%

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Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

Velegalati

Kaps

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Abstract-Implementations of mathematically secure cryptographic algorithms leak information through side channels during run time. Differential Power Analysis (DPA) attacks exploit power leakage to obtain the secret information. Dynamic and Differential Logic (DDL), one of the popular countermeasures against DPA attacks, tries to achieve constant power consumption thereby decorrelating the leakage with the data being processed. Separated Dynamic and Differential Logic (SDDL), a variant of DDL, achieves this goal by duplicating the original design into Direct and Complementary parts which exhibit constant switching activity per clock cycle and have balanced net delays. Traditionally, on Field Programmable Gate Arrays (FPGAs) both parts are placed side-by-side to ensure symmetrical routing. However, due to process variations both parts will have slightly different delays. This limits the effectiveness of SDDL.In this paper we introduce a design flow to achieve interleaved placement of SDDL designs on Xilinx Spartan-3E FPGAs while preserving symmetric routing. We explore several placement configurations with respect to routing and security. The results of our experiments show that a wellbalanced placement of SDDL can double the effectiveness of the SDDL countermeasures on FPGAs.

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High-Level Synthesis for Minimizing Power Side-Channel Information Leakage

Konigsmark

Ren

Wong

et al. 2021

Behavioral Synthesis for Hardware Security

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DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs

Cited by 10 publications

References 18 publications

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic

Techniques to enable the use of Block RAMs on FPGAS with Dynamic and Differential Logic

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

High-Level Synthesis for Minimizing Power Side-Channel Information Leakage

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