Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

Velegalati, Rajesh; Kaps, Jens-Peter

doi:10.1109/fpl.2011.100

Cited by 9 publications

(5 citation statements)

References 15 publications

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“…It has the highest efficiency in resource usage, however the starting edge of the evaluation phase swings depending on the input combination. In [13], authors explored place and route techniques for SDDL logic, which keeps identical routing for both rails in interleaved placement, while EPE problem is not solved yet.…”

Section: Previous Work Related With Epe Protectionmentioning

confidence: 99%

“…Different placement types can be used for an interleaved dual core module. Similar to the work in [13], we investigated several placement types, as shown in Figure 5, due to the merits that type A and B give the smallest distance between complementary instances and nets with high placement density. Comparatively, type C offers a larger space for routing, whereas with lower placement density.…”

Section: Interleaved Placementmentioning

confidence: 99%

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An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

Torre

Riesgo

2012

Constructive Side-Channel Analysis and Secure Design

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Abstract. Early propagation effect (EPE) is a critical problem in conventional dual-rail logic implementations against Side Channel Attacks (SCAs). Among previous EPE-resistant architectures, PA-DPL logic offers EPE-free capability at relatively low cost. However, its sepárate dual core structure is a weakness when facing concentrated EM attacks where a tiny EM probé can be precisely positioned closer to one of the two cores. In this paper, we present an PA-DPL dual-core interleaved structure to strengthen resistance against sophisticated EM attacks on Xilinx FPGA implementations. The main merit of the proposed structure is that every two routing in each signal pair are kept identical even the dual cores are interleaved together. By minimizing the distance between the complementary routings and instances of both cores, even the concentrated EM measurement cannot easily distinguish the minor EM field unbalance. In PA-DPL, EPE is avoided by compressing the evaluation phase to a small portion of the clock period, therefore, the speed is inevitably limited. Regarding this, we made an improvement to extend the duty cycle of evaluation phase to more than 40 percent, yielding a larger máximum working frequency. The detailed design flow is also presented. We validate the security improvement against EM attack by implementing a simplified AES co-processor in Virtex-5 FPGA.

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Section: Previous Work Related With Epe Protectionmentioning

confidence: 99%

Section: Interleaved Placementmentioning

confidence: 99%

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

Torre

Riesgo

2012

Constructive Side-Channel Analysis and Secure Design

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“…Thus, the resource for the CLB block will not be used when routing the T part. This technique exclusively reserves the routing resource for the F logic, but it is not automated because the failed nets after 'sanity check [33]' need to be manually corrected. As well, dummy macros also need to be prepared, and implementation to different devices requires starting work from scratch.…”

Section: Identical Routing Techniquesmentioning

confidence: 99%

“…In [33], authors use dummy hard-macros to preoccupy the CLBs that would later be used to place the (F) rails. By this method, all the driver (input) pins and load (output) pins for CLB included in the blocking macro are disabled.…”

Section: Identical Routing Techniquesmentioning

confidence: 99%

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Bhasin

Otero

et al. 2015

IET Information Security

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Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

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“…This is electrically unallowable and triggers error when converting design from xdl to NCD, immediately before bitstream generation. In [87], authors explored a technique to create dummy CLB hard macros, where all driver (Input) pins and load (Output) pins for this CLB are disabled, to block the CLB's occupation by F rail. By this way, the resource for this CLB block will not be used when auto-routing the original T design.…”

Section: Routing Conflictsmentioning

confidence: 99%

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

He¹

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IXclassical implementations barely satisfy these needs and inevitably stunt the prototype.In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate-or routing-constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next:  Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style.  A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations.  Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. X  Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner.The thesis chapters are organized as follows:Chapter...

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Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

Cited by 9 publications

References 15 publications

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

Sophisticated security verification on routing repaired balanced cell‐based dual‐rail logic against side channel analysis

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

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