2012
DOI: 10.1109/ted.2012.2212442
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Doping, Tunnel Barriers, and Cold Carriers in InAs and InSb Nanowire Tunnel Transistors

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Cited by 17 publications
(11 citation statements)
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“…The reason for such difference in transfer characteristics lies in the fact that, in longer channel length devices ( L CH ≥ 10 nm) the transport is dominated by “cold carrier injection” whereas in shorter length devices, it is controlled by “voltage controlled tunneling” 59 . As pointed out in 59 and also what we find in Fig. 4(a), (b) is that, “voltage controlled tunneling” does not have significant effect on the lowering of SS below the Boltzmann limit and does not vary considerably with gate voltage.…”
Section: Resultsmentioning
confidence: 99%
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“…The reason for such difference in transfer characteristics lies in the fact that, in longer channel length devices ( L CH ≥ 10 nm) the transport is dominated by “cold carrier injection” whereas in shorter length devices, it is controlled by “voltage controlled tunneling” 59 . As pointed out in 59 and also what we find in Fig. 4(a), (b) is that, “voltage controlled tunneling” does not have significant effect on the lowering of SS below the Boltzmann limit and does not vary considerably with gate voltage.…”
Section: Resultsmentioning
confidence: 99%
“…The crossing over of the band edges is resposible for the “low-pass filtering” of the high energy tails of the Fermi distribution function 60 of the source side. As a result, in the low V G regime, transport in long channel TFET is determined by the “cold carrier injection” 59 which entails the 59 , 60 , where Δ ϕ = E v,S − E c,CH . From our calculations it is found that, Δ ϕ ≈ 0.01 eV in HSE TFET and 0.001 eV in PBE TFET.…”
Section: Resultsmentioning
confidence: 99%
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“…Then, the occurrence of tails becomes questionable and only an atomistic approach, like tight-binding NEGF, is able to correctly simulate the effect. 12,13 ACKNOWLEDGMENTS This work was supported by the European Communitys Seventh Frame-work Programme under Grant 619509 through Project E2SWITCH.…”
Section: Discussionmentioning
confidence: 99%
“…Si [29] Si [26] s-Si [31] 16 nm FinFET [10] Si, Ghandi (NUS) 16 Figure 6: Simulated TFET subthreshold swing versus drain current per micron from [8]. The TFETs simulations are from Agarwal [16], Avci [17,18], Sylvia [19], Lu [20], Pillai [21], Koswatta [22], Zhang [23,24], Li [25], with FinFET data from Wu [13]. Simulations in [8] show the potential of the TFET relative to CMOS, however significantly more study is needed to understand the effects of band tails [26] due to phonons and heavy-doping, defect-assisted tunneling [27,28], and interface and border traps.…”
Section: State Of the Artmentioning
confidence: 99%