“…Si [29] Si [26] s-Si [31] 16 nm FinFET [10] Si, Ghandi (NUS) 16 Figure 6: Simulated TFET subthreshold swing versus drain current per micron from [8]. The TFETs simulations are from Agarwal [16], Avci [17,18], Sylvia [19], Lu [20], Pillai [21], Koswatta [22], Zhang [23,24], Li [25], with FinFET data from Wu [13]. Simulations in [8] show the potential of the TFET relative to CMOS, however significantly more study is needed to understand the effects of band tails [26] due to phonons and heavy-doping, defect-assisted tunneling [27,28], and interface and border traps.…”