Doping profile dependence of the vertical impact ionization MOSFET’s (I-MOS) performance

Abelein, Ulrich; Assmuth, Andreas; Iskra, P.; Schindler, Markus; Sulima, T.; Eisele, I.

doi:10.1016/j.sse.2007.06.017

Cited by 29 publications

(20 citation statements)

References 7 publications

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“…Instead, the holes generated by impact ionization charge the floating p-body and cause a dynamic reduction of the threshold voltage, which leads to an extremely fast rising drain current in the subthreshold region. In [31], a very good subthreshold slope of 1.06 mV/dec at V D = 2.25 V has been obtained. Moreover, this device offers the mechanisms for mitigating the damages from hot electrons almost completely [30] and shows the capability of working properly under high temperatures [32].…”

Section: Introductionmentioning

confidence: 79%

“…The high doping of the delta layer, which creates a large potential barrier, makes it possible to achieve high electric fields in the intrinsic zone near the drain without applying a very high drain-source voltage. Moreover, the static leakage current can be suppressed to the range of pA [31]. The doping profile of the device is shown in Fig.…”

Section: Device Structurementioning

confidence: 99%

“…The HD simulator in this work, which is a part of the device simulator GALENE III [43], has been shown in [33] to be able to give very reliable results compared with the experimental data from [31] for the RSi-IMOS. In addition, it was pointed out that the simpler drift-diffusion model cannot reproduce the typical effects of the vertical IMOS with sufficient accuracy.…”

Section: Hydrodynamic Simulatormentioning

confidence: 99%

“…In an attempt to reduce this voltage, the vertical IMOS, which is a planar-doped barrier MOSFET with a floating body, has been introduced and investigated extensively by experiments [29][30][31][32]. This vertical IMOS is not based on avalanche breakdown like the lateral IMOS.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Investigation of the performance of strained-SiGe vertical IMOS-transistors

Dinh

Kraus

Jungemann

2010

Solid-State Electronics

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Section: Introductionmentioning

confidence: 79%

Section: Device Structurementioning

confidence: 99%

Section: Hydrodynamic Simulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Investigation of the performance of strained-SiGe vertical IMOS-transistors

Dinh

Kraus

Jungemann

2010

Solid-State Electronics

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“…[8][9]. It shows excellent subthreshold slope of 4 mV/dec and suppress leakage current efficiently at high temp as well as a very good I ON /I OFF current ratio.…”

Section: Introductionmentioning

confidence: 98%

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (δp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.

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DNA‐Based Strategies for Site‐Specific Doping

Bai

et al. 2020

Adv Funct Materials

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The development of novel doping strategies compatible with high‐resolution patterning and low cost, large‐scale manufacturing is critical to the future development of electronic devices. Here, an approach to achieve nanoscale site‐specific doping of Si wafer using DNA as both the template and the dopant carrier is reported. Upon thermal treatment, the phosphorous atoms in the DNA diffuse into Si wafer, resulting in doping within the region right around the DNA template. A doping length of 30 nm is achieved for 10 s of thermal treatment at 1000 °C. Prototype field effect transistors are fabricated using the DNA‐doped Si substrate; the device characteristics confirmed that the Si is n‐doped. It is also shown that this approach can be extended to achieve both n‐type and p‐type site‐specific doping of Si by using DNA nanostructures to pattern self‐assembled monolayers. This work shows that the DNA template is a dual‐use template that can both pattern Si and deliver dopants.

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Doping profile dependence of the vertical impact ionization MOSFET’s (I-MOS) performance

Cited by 29 publications

References 7 publications

Investigation of the performance of strained-SiGe vertical IMOS-transistors

Investigation of the performance of strained-SiGe vertical IMOS-transistors

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

DNA‐Based Strategies for Site‐Specific Doping

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