Doping-free complementary WSe2 circuit via van der Waals metal integration

Abstract

Two-dimensional (2D) semiconductors have attracted considerable attention for the development of ultra-thin body transistors. However, the polarity control of 2D transistors and the achievement of complementary logic functions remain critical challenges. Here, we report a doping-free strategy to modulate the polarity of WSe 2 transistors using same contact metal but different integration methods. By applying low-energy van der Waals integration of Au electrodes, we observed robust and optimized p-type transistor behavior, which is in great contrast to the transistors fabricated on the same WSe 2 flake using conventional deposited Au contacts with pronounced n-type characteristics. With the ability to switch majority carrier type and to achieve optimized contact for both electrons and holes, a doping-free logic inverter is demonstrated with higher voltage gain of 340, at the bias voltage of 5.5 V. Furthermore, the simple polarity control strategy is extended for realizing more complex logic functions such as NAND and NOR.

Low‐Power Complementary Inverter with Negative Capacitance 2D Semiconductor Transistors

“…For the Schottky barrier FETs, the current in the subthreshold region mainly depends on the thermionic emission current and the thermally-assisted tunneling current. [4,21,34] When the back-gate voltage (V g ) is below the flat-band voltage (V FB ), the thermionic emission current dominates the drain current. The thermionic emission current can be described according to Equation (1)…”

“…A gain larger than 1 is important for cascade logic application because it makes the circuit regenerative and robust to errors. [21] Figure 5d is the static current of the inverter from the V dd to the ground. When the V dd is 0.5 V, we get the highest static current of 127 pA in the forward sweep.…”

“…For a CMOS logic unit, the n-branch will result in high static current and increase power consumption. [21] SS is extracted for both sweep direction of forward sweep (SS Forward ) and reverse sweep (SS Reverse ). The minimum of the SS Reverse is 27 mV dec −1 and the SS Forward is 88 mV dec −1 .…”

“…CMOS logic dissipates less static power than transistor‐transistor logic or NMOS logic because of the low static current, and is one of the most used technologies in VLSI chips. [ 5,8,19–21 ] The construction of complementary circuits requires both n‐ and p‐type unipolar FETs. However, most of TMD semiconductors (MoS 2 , WS 2 , etc.)…”

“…exhibit n‐type characteristics, because dichalcogenides vacancies act as n‐type dopant. [ 21–28 ] Even for tungsten diselenide (WSe 2 ) with balanced conduction and valence band edges, it usually exhibits ambipolar transport characteristics without doping. [ 2,5,8,29 ] Thus, it is of great importance to fabricate unipolar p‐type TMD semiconductors FETs to achieve complementary NCFET in a controllable manner.…”