Low-cost supercomputer performance can be achieved through parallelism. Parallel computers with fixed nodes are easy to build but the mapping of software onto such systems is computationally very expensive. By uslng reconfigureable nodes the complexity of the user software is reduced immensely. This however produces the problem of guaranteeing a completely reconfigureable system that can connect any node to any node under all circumstances. The MC2/64 machine is a distributed parallel machine using the lnmos Transputer and based on the concept of reconfigureable nodes. This paper describes the architecture, configuration and the system software of MC2/64. The ever increasing demand for microcomputer power is being satisfied at this moment by two areas of technological development namely high-speed RlSC technology and parallel processing. RlSC technology offers the promise of systems with impressive performance and it requires little change in the way the software is developed, but the technology is reaching its performance limits. Parallel processing promises systems whose computing power is limited only by the resources of the system designer and the ingenuity of the programmer! By using RlSC in parallel we can achieve remarkable microcomputer performance at a much lower cost.The lnmos transputer is a high-performance 32-bit (almost) RlSC processor with a unique communications-based architecture designed for parallel processing systems using a distributed memory, message-passing model. Transputers communicate through links. The choice of point-to-point communication links means that a system can be constructed from an arbitrary number of transputers. As the number of transputers in the system increases, the total processing power, memory bandwidth and communication bandwidth of the system grow proportionally.The Massively Concurrent Computer (MC2) project was initiated to exploit the new technological developments around parallel processing and build a multi-user, low-cost, high-performance parallel computer centered around the transputer and based on the concept of reconfigureable transputer nodes.CH2867-0/90/0000/0097$01 .OO 0 1990 IEEE
97The first phase of the MC2 project involved the building and testing of the initial hardware. For the second phase a single user system consisting of up to sixteen transputers in a completely reconfigureable cluster was completed. The intention of the third phase of the pro'ect are multi-user 64 using the existing hardware and clusters.Envisaged completion of this phase is end of April 1991. The MC2/64 machine has actually been completed and two experimental systems are currently in use. This paper will be divided into two sections. The first section will give an overview of the MC2/64 machine architecture and a description of the techniques that are used to configure the machine. The second section will describe the system software as well as the design methodology used to develop the system software. and 256 processor systems (the MC tr /64 and MC2/256) MC2/64 ARCHITECTURE ...