Proceedings of the 44th Annual International Symposium on Computer Architecture 2017
DOI: 10.1145/3079856.3080209
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Do-It-Yourself Virtual Memory Translation

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Cited by 40 publications
(23 citation statements)
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“…Use of large pages to increase TLB-coverage [34,35,36,55,57,63,64,66] and additional MMU structures to cache multiple levels of the page-tables [19,24,26] are some of the techniques widely adopted in commercial systems. In addition, researchers have also proposed TLB-speculation [20,60], prefetching translations [47,53,62], eliminating or devirtualizing virtual memory [42], or exposing virtual memory system to applications to make the case for application-specific address translation [16].…”
Section: Virtual Memorymentioning
confidence: 99%
See 1 more Smart Citation
“…Use of large pages to increase TLB-coverage [34,35,36,55,57,63,64,66] and additional MMU structures to cache multiple levels of the page-tables [19,24,26] are some of the techniques widely adopted in commercial systems. In addition, researchers have also proposed TLB-speculation [20,60], prefetching translations [47,53,62], eliminating or devirtualizing virtual memory [42], or exposing virtual memory system to applications to make the case for application-specific address translation [16].…”
Section: Virtual Memorymentioning
confidence: 99%
“…An important feature of Mitosis is that it requires no changes to applications or hardware, and is easy to use on a perapplication basis. For this reason, Mitosis is readily deployable and complementary to emerging hardware techniques to reduce address translation overheads like segmentation [21,49], PTE coalescing [58,59] and user-managed virtual memory [16]. We will release our implementation of Mitosis to enable future research on page-table placement and plan to upstream our changes to Linux.…”
Section: Introductionmentioning
confidence: 99%
“…Huge pages have become vital for mitigating address translation overheads of modern workloads as non-linear scaling of the hardware cost, energy consumption and lookup latency has impacted the growth of TLB capacity [40,49,63]. Though each address translation may require up to 6× more memory lookups in virtualized systems due to the two-dimensional page tables [31], modern hardware can nearly match the address translation efficiency of virtualized environments with the native systems by utilizing huge pages [61].…”
Section: Motivationmentioning
confidence: 99%
“…Address translation overhead has become a major performance bottleneck for modern data processing applications as TLB scaling has not caught up with the growth of memory capacity in recent times [31,40,49,63]. This has inspired support for huge pages in most processors [4,5,53].…”
Section: Introductionmentioning
confidence: 99%
“…With the continuously increasing application footprints and a corresponding growth of memory capacity, virtual-tophysical memory address translation tends to be a new bottleneck of system performance [8]. Modern computer systems typically employ translation lookaside buffer (TLB) as a cache to store the recent virtual-to-physical address translations for faster retrieval in the future.…”
Section: Introductionmentioning
confidence: 99%