Distributed hierarchical processing

DePesa, Paul; Keogan, Danny

doi:10.1117/12.476932

Cited by 11 publications

(2 citation statements)

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“…Distributed computing hardware has become the de facto remedy for this problem [2][3][4][5][6][7][8][9][11][12][13][14][15]. Given the cost effectiveness of systems assembled from smaller two and four CPU computers, distributed computing has become commonplace in modern semiconductor manufacturing.…”

Section: Introductionmentioning

confidence: 99%

Distributed computing in mask data preparation for 45-nm node and below

2006

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Data Preparation for photomask manufacturing is characterized by computational complexity that grows faster than the evolution of computer processor ability. Parallel processing generally addresses this problem and is an accepted mechanism for preparing mask data. One judges a parallel software implementation by total time, stability and predictability of computation. We apply several fundamental techniques to dramatically improve these metrics for a parallel, distributed MDP system. This permits the rapid, predictable computation of the largest mask layouts on conventional computing clusters.

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Section: Introductionmentioning

confidence: 99%

Distributed computing in mask data preparation for 45-nm node and below

2006

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“…Design trends indicate that for performance enhancements in data storage and data processing larger and larger arrays are going to be incorporated into designs [2]. The benefits of hierarchy for data processing have been largely discussed in literature [1,[3][4][5][6]. It provides for the smallest file size and the fastest processing time.…”

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confidence: 97%

The prospects for hierarchical data processing with growing complexity of the post-tapeout flow

Schulze

Sahouria

2005

Design and Process Integration for Microelectronic Manufacturing III

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The drive of the semiconductor industry towards smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making. The wavelength gap in lithography and process effects as well as dependencies on the design content have led to the tremendous variety of resolution enhancement techniques and process correction approaches that are currently applied to a design on its path to manufacturing. As the 65nm nodes become production ready and the 45nm node shifts into the focus of the development effects like flare in wafer exposure, fogging effects in ebeam mask exposure and others that previously could be ignored are becoming significant so that their correction prior to manufacturing is required. That means additional correction steps are necessary to complete the data preparation. These put a larger burden on the data processing path and raise concerns over data volume and processing time limitations. Hierarchical processing methods have proven very effective in the past to keep data volumes and processing time in control. The paper explores the design trends and the potential of hierarchical processing under the new circumstances. Extended data flows with a variety of correction steps are investigated. Experimental results that demonstrate the benefit of hierarchical methods in conjunction with parallel processing methods like multithreading and distributed processing are provided. The benefit of introducing more effective data formats like OASIS in these flows will be illustrated.Historically the completion of a design was marked by the full chip verification and the delivery of a DRC an LVS clean layout. The transition of the data in form of GDSII into the mask writer format was usually a simple two step process -application of a general process bias (combination of mask and wafer lithography) and fracturing/formatting. The implementation of this simple flow was frequently shifted from the mask supplier side to the data supplier side since it was not very demanding [1]. A common flow as it is encountered today looks quite different. Figure 1 gives an example of a typical sequence as encountered in 90nm or 65nm data flows. The complexity is largely driven by the variety of processing effects that require data correction -CMP and etch processes drive the need for leveling pattern density via fill or slotting. These structures are printable elements and are inserted into the layout as part of the preprocessing prior to corrections for the imaging. A next step is rules based data corrections. This includes the insertion of non-printable assist-features for process window improvement for isolated features as well as other rules based corrections like a table driven OPC or target correction. Alternately, a phase shifting mask set can be derived to print the design pattern. After the contents of the layout are fully defined the model based OPC is applied. This functional block is followed by verification ste...

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Direct Comparison of Visual Cortex Activation in Human and Nonhuman Primates Using Functional Magnetic Resonance Imaging

Dubowitz

2004

Methods in Enzymology

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Distributed hierarchical processing

Cited by 11 publications

References 0 publications

Distributed computing in mask data preparation for 45-nm node and below

Distributed computing in mask data preparation for 45-nm node and below

The prospects for hierarchical data processing with growing complexity of the post-tapeout flow

Direct Comparison of Visual Cortex Activation in Human and Nonhuman Primates Using Functional Magnetic Resonance Imaging

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