Distance constrained dimensionality reduction for parametric fault test generator

Gomes, Alfred; Chatterjee, Abhijit

doi:10.1109/ats.2001.990318

Cited by 3 publications

(1 citation statement)

References 15 publications

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“…The method proposed in [9] tries to predict performances based on models built on the correlation of the output parameters. In [10] a fast exploration of the functional test space is used to determine redundancy in functional tests. Machine learning has also been used recently in [11] to learn the intricate mappings between a subset of functional tests and direct pass/fail decisions.…”

Section: Previous Workmentioning

confidence: 99%

Analog performance prediction based on archimedean copulas generation algorithm

Beznia¹,

Bounceur²,

Euler³

2011

2011 IEEE 6th International Design and Test Workshop (IDT)

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Testing analog circuits is a complex and very time consuming task. In contrary to digital circuits, testing analog circuits needs different configurations, each of them targets a certain set of output parameters which are the performances and the test measures. One of the solutions to simplify the test task and optimize test time is the reduction of the number of tobe-tested performances by eliminating redundant ones. However, the main problem with such a solution is the identification of redundant performances. Traditional methods based on calculation of the correlation between different performances or on the defect level are shown to be not sufficient. This paper presents a new method based on the Archimedean copula generation algorithm. It predicts the performance value from each output parameter value based on the dependence (copula) between the two values. Therefore, different performances can be represented by a single output parameter; as a result, less test configurations are required. To validate the proposed approach, a CMOS imager with two performances and one test measure is used. The simulation results show that the two performances can be replaced by a single test measure. Industrial results are also reported to prove the superiority of the proposed approach. 1

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Section: Previous Workmentioning

confidence: 99%

Analog performance prediction based on archimedean copulas generation algorithm

Beznia¹,

Bounceur²,

Euler³

2011

2011 IEEE 6th International Design and Test Workshop (IDT)

View full text Add to dashboard Cite

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Minimization of functional tests by statistical modelling of analogue circuits

Akkouche

Bounceur

Mir

et al. 2007

2007 International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

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Ordering of analog specification tests based on parametric defect level estimation

Akkouche

Mir

Simeu

2010

2010 28th VLSI Test Symposium (VTS)

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ISBN 978-1-4244-6649-8International audienceThis paper presents an approach for ordering analog specification (or functional) tests that is based on a statistical estimation of parametric defect level. A statistical model of n specification tests is obtained by applying a density estimation technique to a small sample of data (obtained from the initial phase of production testing or through Monte-Carlo simulation of the design). The statistical model is next sampled to generate a large population of synthetic devices from which specification tests can be ordered according to their impact on defect level by means of feature selection techniques. An optimal order can be obtained using the Branch and Bound method when n is relatively low. However, for larger values of n, heuristic methods such as genetic algorithms and floating search must be used which do not guarantee an optimal order. Since the value of n can reach several hundreds for advanced analog integrated devices, we have studied a heuristic algorithm that considers combinations of subsets of the overall test set. These subsets are easier to model and to order and a heuristic approach is used to form an overall order. This test ordering approach is evaluated for different artificial and experimental case-studies, including a fully differential operational amplifier. These case-studies are simple enough so that it is possible to compare the results obtained with the algorithm with an expected reference order

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Distance constrained dimensionality reduction for parametric fault test generator

Cited by 3 publications

References 15 publications

Analog performance prediction based on archimedean copulas generation algorithm

Analog performance prediction based on archimedean copulas generation algorithm

Minimization of functional tests by statistical modelling of analogue circuits

Ordering of analog specification tests based on parametric defect level estimation

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